From be06ed50cb95b7690e1743e1913f11e811efb611 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Thu, 9 May 2024 02:10:45 +0200 Subject: [PATCH] if top level schematic has an associated symbol (.sym) file ensure their ports match, otherwise issue an error. if netlisting fails return non zero exit code if netlisting from command line --- src/globals.c | 1 + src/netlist.c | 17 +++++++++++----- src/spice_netlist.c | 17 +++++++++++----- src/tedax_netlist.c | 6 ++++-- src/verilog_netlist.c | 6 ++++-- src/vhdl_netlist.c | 6 ++++-- src/xinit.c | 2 +- src/xschem.h | 3 ++- tests/xschemtest.tcl | 2 +- .../inst_sch_select/comp3_empty.sch | 8 +++++++- .../inst_sch_select/inst_sch_select.sch | 20 +++++++++---------- 11 files changed, 58 insertions(+), 30 deletions(-) diff --git a/src/globals.c b/src/globals.c index 0d8cf66c..17a7e036 100644 --- a/src/globals.c +++ b/src/globals.c @@ -171,6 +171,7 @@ int debug_var=-10; /* will be set to 0 in xinit.c */ int help=0; /* help option set to global scope, printing help is deferred */ /* when configuration xschemrc has been read 20140406 */ FILE *errfp = NULL; +int exit_code = 0; /* success */ char home_dir[PATH_MAX]; /* home dir obtained via getpwuid */ char user_conf_dir[PATH_MAX]; char sel_file[PATH_MAX]=""; diff --git a/src/netlist.c b/src/netlist.c index a48dfa2d..617929a0 100644 --- a/src/netlist.c +++ b/src/netlist.c @@ -1570,12 +1570,13 @@ int warning_overlapped_symbols(int sel) return err; } -int sym_vs_sch_pins() +/* all: -1: check all symbols, otherwise check only indicated symbol */ +int sym_vs_sch_pins(all) { int err = 0; char **lab_array =NULL; int lab_array_size = 0; - int i, j, k, symbol, n_syms, pin_cnt=0, pin_match, mult; + int i, j, k, symbol, pin_cnt=0, pin_match, mult; struct stat buf; char name[PATH_MAX]; char *type = NULL; @@ -1591,8 +1592,14 @@ int sym_vs_sch_pins() char tag[1]; char filename[PATH_MAX]; char f_version[100]; - n_syms = xctx->symbols; - for(i=0;isymbols; + int n_syms = xctx->symbols; + if(all >= 0 && all < xctx->symbols) { + start = all; + end = all + 1; + } + for(i = start; i < end; ++i) { if( xctx->sym[i].type && !strcmp(xctx->sym[i].type,"subcircuit")) { int rects = xctx->sym[i].rects[PINLAYER]; @@ -1849,6 +1856,6 @@ int sym_vs_sch_pins() my_free(_ALLOC_ID_, &pin_dir); } /* for(i=0;isymbols > n_syms) remove_symbol(xctx->symbols - 1); + if(all == -1) while(xctx->symbols > n_syms) remove_symbol(xctx->symbols - 1); return err; } diff --git a/src/spice_netlist.c b/src/spice_netlist.c index fe298e74..487997b4 100644 --- a/src/spice_netlist.c +++ b/src/spice_netlist.c @@ -272,8 +272,12 @@ int global_spice_netlist(int global) /* netlister driver */ int save_prev_mod = xctx->prev_set_modify; struct stat buf; char *top_symbol_name = NULL; - int found_top_symbol = 0; /* if top level has a symbol use it for pin ordering */ + /* if top level has a symbol use it for pin ordering + * top_symbol_name == 1: a symbol file matching schematic has been found. + * top_symbol_name == 3: the found symbol has type=subcircuit and has ports */ + int found_top_symbol = 0; + exit_code = 0; /* reset exit code */ split_f = tclgetboolvar("split_files"); dbg(1, "global_spice_netlist(): invoking push_undo()\n"); xctx->push_undo(); @@ -342,18 +346,20 @@ int global_spice_netlist(int global) /* netlister driver */ if(!stat(top_symbol_name, &buf)) { /* if top level has a symbol use the symbol for pin ordering */ dbg(1, "found top level symbol %s\n", top_symbol_name); load_sym_def(top_symbol_name, NULL); + found_top_symbol = 1; /* only use the symbol if it has pins and is a subcircuit */ if(xctx->sym[xctx->symbols - 1].type != NULL && !strcmp(xctx->sym[xctx->symbols - 1].type, "subcircuit") && xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) { fprintf(fd," "); print_spice_subckt_nodes(fd, xctx->symbols - 1); - found_top_symbol = 1; + found_top_symbol = 3; + err |= sym_vs_sch_pins(xctx->symbols - 1); } remove_symbol(xctx->symbols - 1); } my_free(_ALLOC_ID_, &top_symbol_name); - if(!found_top_symbol) { + if(found_top_symbol != 3) { for(i=0;iinstances; ++i) { if(skip_instance(i, 1, lvs_ignore)) continue; my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type); @@ -493,6 +499,8 @@ int global_spice_netlist(int global) /* netlister driver */ xctx->currsch--; unselect_all(1); dbg(1, "global_spice_netlist(): invoking pop_undo(0, 0)\n"); + /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ + err |= sym_vs_sch_pins(-1); if(!tclgetboolvar("keep_symbols")) remove_symbols(); xctx->pop_undo(4, 0); xctx->prev_set_modify = save_prev_mod; @@ -505,8 +513,6 @@ int global_spice_netlist(int global) /* netlister driver */ my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name)); dbg(1, "spice_netlist(): invoke prepare_netlist_structs for %s\n", xctx->current_name); err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */ - /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ - err |= sym_vs_sch_pins(); if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets; my_free(_ALLOC_ID_, ¤t_dirname_save); } @@ -584,6 +590,7 @@ int global_spice_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &place); xctx->netlist_count = 0; tclvareval("show_infotext ", my_itoa(err), NULL); /* critical error: force ERC window showing */ + exit_code = err; return err; } diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c index 852f4d61..8c712217 100644 --- a/src/tedax_netlist.c +++ b/src/tedax_netlist.c @@ -137,6 +137,7 @@ int global_tedax_netlist(int global) /* netlister driver */ int lvs_ignore = tclgetboolvar("lvs_ignore"); int save_prev_mod = xctx->prev_set_modify; + exit_code = 0; /* reset exit code */ xctx->push_undo(); statusmsg("",2); /* clear infowindow */ str_hash_init(&subckt_table, HASHSIZE); @@ -244,6 +245,8 @@ int global_tedax_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &xctx->sch[xctx->currsch]); xctx->currsch--; unselect_all(1); + /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ + err |= sym_vs_sch_pins(-1); if(!tclgetboolvar("keep_symbols")) remove_symbols(); xctx->pop_undo(4, 0); xctx->prev_set_modify = save_prev_mod; @@ -256,8 +259,6 @@ int global_tedax_netlist(int global) /* netlister driver */ my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name)); err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */ - /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ - err |= sym_vs_sch_pins(); if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets; my_free(_ALLOC_ID_, ¤t_dirname_save); } @@ -287,6 +288,7 @@ int global_tedax_netlist(int global) /* netlister driver */ if(!debug_var) xunlink(netl_filename); xctx->netlist_count = 0; tclvareval("show_infotext ", my_itoa(err), NULL); /* critical error: force ERC window showing */ + exit_code = err; return err; } diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c index 462273a2..a76d811b 100644 --- a/src/verilog_netlist.c +++ b/src/verilog_netlist.c @@ -98,6 +98,7 @@ int global_verilog_netlist(int global) /* netlister driver */ int lvs_ignore = tclgetboolvar("lvs_ignore"); int save_prev_mod = xctx->prev_set_modify; + exit_code = 0; /* reset exit code */ split_f = tclgetboolvar("split_files"); xctx->push_undo(); xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */ @@ -365,6 +366,8 @@ int global_verilog_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &xctx->sch[xctx->currsch]); xctx->currsch--; unselect_all(1); + /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ + err |= sym_vs_sch_pins(-1); if(!tclgetboolvar("keep_symbols")) remove_symbols(); xctx->pop_undo(4, 0); xctx->prev_set_modify = save_prev_mod; @@ -376,8 +379,6 @@ int global_verilog_netlist(int global) /* netlister driver */ } my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name)); err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */ - /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ - err |= sym_vs_sch_pins(); if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets; my_free(_ALLOC_ID_, ¤t_dirname_save); } @@ -407,6 +408,7 @@ int global_verilog_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &type); xctx->netlist_count = 0; tclvareval("show_infotext ", my_itoa(err), NULL); /* critical error: force ERC window showing */ + exit_code = err; return err; } diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c index e3c50f60..4c278d1b 100644 --- a/src/vhdl_netlist.c +++ b/src/vhdl_netlist.c @@ -123,6 +123,7 @@ int global_vhdl_netlist(int global) /* netlister driver */ int lvs_ignore = tclgetboolvar("lvs_ignore"); int save_prev_mod = xctx->prev_set_modify; + exit_code = 0; /* reset exit code */ split_f = tclgetboolvar("split_files"); xctx->push_undo(); xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */ @@ -454,6 +455,8 @@ int global_vhdl_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &xctx->sch[xctx->currsch]); xctx->currsch--; unselect_all(1); + /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ + err |= sym_vs_sch_pins(-1); if(!tclgetboolvar("keep_symbols")) remove_symbols(); xctx->pop_undo(4, 0); xctx->prev_set_modify = save_prev_mod; @@ -465,8 +468,6 @@ int global_vhdl_netlist(int global) /* netlister driver */ } my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name)); err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */ - /* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */ - err |= sym_vs_sch_pins(); if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets; my_free(_ALLOC_ID_, ¤t_dirname_save); } @@ -494,6 +495,7 @@ int global_vhdl_netlist(int global) /* netlister driver */ my_free(_ALLOC_ID_, &port_value); xctx->netlist_count = 0; tclvareval("show_infotext ", my_itoa(err), NULL); /* critical error: force ERC window showing */ + exit_code = err; return err; } diff --git a/src/xinit.c b/src/xinit.c index f3df90b2..e0ccdb99 100644 --- a/src/xinit.c +++ b/src/xinit.c @@ -2994,7 +2994,7 @@ int Tcl_AppInit(Tcl_Interp *inter) tcleval("eval_postinit_commands"); if(cli_opt_quit) { - tcleval("exit 0"); + tclvareval("exit ", my_itoa(exit_code), NULL); } diff --git a/src/xschem.h b/src/xschem.h index ad54156b..780efda7 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -1191,6 +1191,7 @@ extern int fix_mouse_coord; extern int help; extern char *cad_icon[]; extern FILE *errfp; +extern int exit_code; extern char home_dir[PATH_MAX]; /* home dir obtained via getpwuid */ extern char user_conf_dir[PATH_MAX]; /* usually ~/.xschem */ extern char sel_file[PATH_MAX]; @@ -1482,7 +1483,7 @@ extern void clear_partial_selected_wires(void); extern int connect_by_kissing(void); extern int unselect_partial_sel_wires(void); extern void delete_files(void); -extern int sym_vs_sch_pins(void); +extern int sym_vs_sch_pins(int all); extern char *get_generator_command(const char *str); extern int match_symbol(const char name[]); extern int save_schematic(const char *); /* 20171020 added return value */ diff --git a/tests/xschemtest.tcl b/tests/xschemtest.tcl index db76ec0e..587eb1d1 100644 --- a/tests/xschemtest.tcl +++ b/tests/xschemtest.tcl @@ -194,7 +194,7 @@ proc netlist_test {} { greycnt.sch verilog 2899796185 autozero_comp.sch spice 2741955505 test_generators.sch spice 49312823 - inst_sch_select.sch spice 1539700121 + inst_sch_select.sch spice 337090690 test_bus_tap.sch spice 188702715 loading.sch vhdl 2975204502 mos_power_ampli.sch spice 3405708328 diff --git a/xschem_library/inst_sch_select/comp3_empty.sch b/xschem_library/inst_sch_select/comp3_empty.sch index d6e33d55..4f02ea75 100644 --- a/xschem_library/inst_sch_select/comp3_empty.sch +++ b/xschem_library/inst_sch_select/comp3_empty.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -25,3 +25,9 @@ V {} S {vout out 0 2} E {} C {architecture.sym} 70 -610 0 0 { nothing here, use global schematic properties } +C {ipin.sym} 120 -550 0 0 {name=p161 lab=PLUS} +C {ipin.sym} 120 -500 0 0 {name=p1 lab=MINUS} +C {opin.sym} 200 -530 0 0 {name=p20 lab=OUT} +C {noconn.sym} 200 -530 0 0 {name=l1} +C {noconn.sym} 120 -550 0 1 {name=l2} +C {noconn.sym} 120 -500 0 1 {name=l3} diff --git a/xschem_library/inst_sch_select/inst_sch_select.sch b/xschem_library/inst_sch_select/inst_sch_select.sch index 0b81eae7..5ad24886 100644 --- a/xschem_library/inst_sch_select/inst_sch_select.sch +++ b/xschem_library/inst_sch_select/inst_sch_select.sch @@ -71,7 +71,7 @@ hilight_wave=-1 color="4 7" node="plus minus"} T {Default instance: -Uses comp3.sch} 320 -950 0 0 0.4 0.4 { layer=7} +Uses comp3.sch} 320 -960 0 0 0.4 0.4 { layer=7} T {Alternate instance: Uses comp3_parax.sch} 10 -960 0 0 0.4 0.4 { layer=8} T {Alternate instance: @@ -86,7 +86,7 @@ spice schematic attribute} 320 -750 0 0 0.4 0.4 { layer=11} T {Alternate instance: Uses spice_sym_def to read in file comp3_file.cir -no schematic used} 330 -450 0 0 0.4 0.4 { layer=12} +no schematic used} 330 -460 0 0 0.4 0.4 { layer=12} T {The same symbol is simulated with 5 different implementations using instance 'schematic' and 'spice_sym_def ' attributes} 30 -1040 0 0 0.4 0.4 { layer=4 slant=oblique} T {Instance based @@ -109,7 +109,7 @@ is provided either directly or by a .include line xschem will adapt port order of instances to match the port order of the provided netlists.} 620 -940 0 0 0.5 0.5 {} -C {comp3.sym} 480 -840 0 0 {name=x1} +C {comp3.sym} 480 -850 0 0 {name=x1} C {comp3.sym} 180 -850 0 0 {name=x2 schematic=comp3_parax.sch} C {comp3.sym} 180 -580 0 0 {name=x3 @@ -152,7 +152,7 @@ verilog_sym_def="verilog stuff" vhdl_sym_def="vhdl stuff"} C {comp3.sym} 480 -580 0 0 {name=x5 schematic=comp3_empty.sch} -C {comp3.sym} 480 -280 0 0 {name=x6 +C {comp3.sym} 480 -290 0 0 {name=x6 schematic=comp3_file spice_sym_def="tcleval( [read_data_nonewline [abs_sym_path comp3_file.cir]] @@ -165,12 +165,12 @@ tclcommand="textwindow [abs_sym_path comp3_file.cir]"} C {comp3_read.sym} 890 -280 0 0 {name=x7 tclcommand="textwindow [abs_sym_path comp3_read.cir]"} -C {lab_pin.sym} 540 -840 0 1 {name=p2 lab=OUT1} +C {lab_pin.sym} 540 -850 0 1 {name=p2 lab=OUT1} C {lab_pin.sym} 240 -850 0 1 {name=p5 lab=OUT2} C {lab_pin.sym} 240 -580 0 1 {name=p8 lab=OUT3} C {lab_pin.sym} 240 -290 0 1 {name=p35 lab=OUT4} C {lab_pin.sym} 540 -580 0 1 {name=p16 lab=OUT5} -C {lab_pin.sym} 540 -280 0 1 {name=p19 lab=OUT6} +C {lab_pin.sym} 540 -290 0 1 {name=p19 lab=OUT6} C {lab_pin.sym} 950 -280 0 1 {name=p23 lab=OUT7} C {lab_pin.sym} 120 -820 0 0 {name=p6 lab=MINUS} C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0} @@ -193,7 +193,7 @@ C {code_shown.sym} 140 -170 0 0 {name=COMMANDS only_toplevel=false value=".contr write test_instance_schematic_selection.raw .endc "} -C {lab_pin.sym} 420 -870 0 0 {name=p1 lab=PLUS} +C {lab_pin.sym} 420 -880 0 0 {name=p1 lab=PLUS} C {lab_pin.sym} 420 -610 0 0 {name=p15 lab=PLUS} C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version released on 2/22/06 @@ -323,15 +323,15 @@ C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version r "} C {lab_pin.sym} 420 -550 0 0 {name=p17 lab=MINUS} C {lab_pin.sym} 120 -880 0 0 {name=p4 lab=PLUS} -C {lab_pin.sym} 420 -310 0 0 {name=p18 lab=PLUS} +C {lab_pin.sym} 420 -320 0 0 {name=p18 lab=PLUS} C {vsource.sym} 700 -120 0 0 {name=V1 value=2 savecurrent=true} -C {lab_pin.sym} 420 -250 0 0 {name=p20 lab=MINUS} +C {lab_pin.sym} 420 -260 0 0 {name=p20 lab=MINUS} C {lab_pin.sym} 120 -610 0 0 {name=p7 lab=PLUS} C {lab_pin.sym} 830 -310 0 0 {name=p22 lab=PLUS} C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC} C {lab_pin.sym} 830 -250 0 0 {name=p24 lab=MINUS} -C {lab_pin.sym} 420 -810 0 0 {name=p3 lab=MINUS} +C {lab_pin.sym} 420 -820 0 0 {name=p3 lab=MINUS} C {lab_pin.sym} 120 -320 0 0 {name=p34 lab=PLUS} C {lab_pin.sym} 120 -550 0 0 {name=p9 lab=MINUS} C {lab_pin.sym} 120 -260 0 0 {name=p36 lab=MINUS}