diff --git a/src/eval_expr.y b/src/eval_expr.y
index 4cc42556..bc91e73b 100644
--- a/src/eval_expr.y
+++ b/src/eval_expr.y
@@ -242,6 +242,7 @@ void eval_expr_init_table(void)  /* puts arithmetic functions in table. */
 void eval_expr_clear_table(void)
 {
   symrec *ptr = sym_table;
+  if(ret) my_free(_ALLOC_ID_, &ret);
   while(ptr) {
     symrec *tmp = ptr;
     ptr = ptr->next;
diff --git a/src/xschem.tcl b/src/xschem.tcl
index d62ba76c..1bdef451 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -4130,6 +4130,7 @@ proc open_sub_schematic {{inst {}} {inst_number 0}} {
   global search_schematic
   set rawfile {}
   set n_sel [xschem get lastsel]
+  set current_win_path [xschem get current_win_path] ;# .drw or .x1.drw or .x2.drw ...
 
   if { $inst eq {} && $n_sel == 0} {
     if {$search_schematic == 1} {
@@ -4153,18 +4154,22 @@ proc open_sub_schematic {{inst {}} {inst_number 0}} {
   if {[xschem raw loaded] >= 0} {
     set rawfile [xschem raw_query rawfile]
     set sim_type [xschem raw_query sim_type]
+    set raw_level [xschem get raw_level]
   }
   set res [xschem schematic_in_new_window force]
+  set new_window_path [xschem get last_created_window] ;# something like .x1.drw
+  xschem copy_hierarchy $current_win_path $new_window_path
   # if successfull descend into indicated sub-schematic
   if {$res} {
     xschem copy_hilights
-    xschem new_schematic switch [xschem get last_created_window]
+    xschem new_schematic switch $new_window_path
     if { $rawfile ne {}} {
       if {$sim_type eq {op}} {
         xschem annotate_op $rawfile
       } else {
         xschem raw_read $rawfile $sim_type
       }
+      xschem set raw_level $raw_level
     }
     xschem select instance $inst fast
     xschem descend
diff --git a/xschem_library/rom8k/lvnot.sch b/xschem_library/rom8k/lvnot.sch
index 5bdb109a..4f96d2df 100644
--- a/xschem_library/rom8k/lvnot.sch
+++ b/xschem_library/rom8k/lvnot.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -34,25 +34,28 @@ generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=st
 verilog_stop=true}
 V {assign #150 y=~a ;}
 S {}
+F {}
 E {}
-P 4 5 350 -380 350 -140 480 -140 480 -380 350 -380 {dash=4}
-T {@name x @m} 353.75 -395 0 0 0.2 0.2 {}
-T {@symname} 486.25 -395 0 1 0.2 0.2 {}
-N 420 -280 420 -240 {lab=y}
+P 4 5 350 -440 350 -70 480 -70 480 -440 350 -440 {dash=4}
+T {@name x @m} 353.75 -455 0 0 0.2 0.2 {}
+T {@symname} 486.25 -455 0 1 0.2 0.2 {}
 N 420 -260 480 -260 {lab=y}
-N 380 -310 380 -210 {lab=a}
+N 380 -370 380 -140 {lab=a}
 N 350 -260 380 -260 {lab=a}
-N 420 -310 470 -310 {lab=VCCPIN}
-N 470 -340 470 -310 {lab=VCCPIN}
-N 420 -340 470 -340 {lab=VCCPIN}
-N 420 -210 470 -210 {lab=VSSPIN}
-N 470 -210 470 -180 {lab=VSSPIN}
-N 420 -180 470 -180 {lab=VSSPIN}
-N 420 -360 420 -340 {lab=VCCPIN}
-N 420 -180 420 -160 {lab=VSSPIN}
+N 420 -370 470 -370 {lab=VCCPIN}
+N 470 -400 470 -370 {lab=VCCPIN}
+N 420 -400 470 -400 {lab=VCCPIN}
+N 420 -140 470 -140 {lab=VSSPIN}
+N 470 -140 470 -110 {lab=VSSPIN}
+N 420 -110 470 -110 {lab=VSSPIN}
+N 420 -420 420 -400 {lab=VCCPIN}
+N 420 -110 420 -90 {lab=VSSPIN}
+N 420 -340 420 -330 {lab=DP}
+N 420 -270 420 -240 {lab=y}
+N 420 -180 420 -170 {lab=DN}
 C {opin.sym} 480 -260 0 0 {name=p1 lab=y verilog_type=wire}
 C {ipin.sym} 350 -260 0 0 {name=p2 lab=a}
-C {use.sym} 300 -540 0 0 {------------------------------------------------
+C {use.sym} 300 -600 0 0 {------------------------------------------------
 library ieee;
         use ieee.std_logic_1164.all;
 --         use ieee.std_logic_arith.all;
@@ -61,9 +64,15 @@ library ieee;
 -- library SYNOPSYS;
 --         use SYNOPSYS.ATTRIBUTES.ALL;
 }
-C {p.sym} 400 -310 0 0 {name=m2 model=cmosp w=wp l=lp  m=1 }
-C {lab_pin.sym} 420 -360 0 0 {name=p149 lab=VCCPIN}
-C {lab_pin.sym} 420 -160 0 0 {name=p3 lab=VSSPIN}
-C {n.sym} 400 -210 0 0 {name=m1 model=cmosn w=wn l=lln m=1}
+C {p.sym} 400 -370 0 0 {name=m2 model=cmosp w=wp l=lp  m=1 }
+C {lab_pin.sym} 420 -420 0 0 {name=p149 lab=VCCPIN}
+C {lab_pin.sym} 420 -90 0 0 {name=p3 lab=VSSPIN}
+C {n.sym} 400 -140 0 0 {name=m1 model=cmosn w=wn l=lln m=1}
 C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
 C {verilog_timescale.sym} 660 -217.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
+C {ammeter.sym} 420 -300 0 0 {name=Vmeas savecurrent=true spice_ignore=0}
+C {ammeter.sym} 420 -210 0 0 {name=Vmeas1 savecurrent=true spice_ignore=0}
+C {lab_pin.sym} 420 -180 0 0 {name=p4 sig_type=std_logic lab=DN}
+C {lab_pin.sym} 420 -330 0 0 {name=p5 sig_type=std_logic lab=DP}
+C {spice_probe.sym} 420 -330 2 0 {name=p95 analysis=tran}
+C {spice_probe.sym} 420 -180 0 1 {name=p6 analysis=tran}