From b7b9d666a9f2abe416e1e8398504d21ef8623849 Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Wed, 23 Dec 2020 18:16:53 +0100 Subject: [PATCH] fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion --- src/spice_netlist.c | 17 ++++++++--------- src/verilog_netlist.c | 23 ++++++++++++----------- src/vhdl_netlist.c | 16 +++++++++------- xschem_library/logic/ram.sch | 3 ++- 4 files changed, 31 insertions(+), 28 deletions(-) diff --git a/src/spice_netlist.c b/src/spice_netlist.c index b04e81c1..57967a4e 100644 --- a/src/spice_netlist.c +++ b/src/spice_netlist.c @@ -346,12 +346,11 @@ void spice_block_netlist(FILE *fd, int i) if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) { my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename)); - load_schematic(1,filename, 0); + spice_stop? load_schematic(0,filename, 0) : + load_schematic(1,filename, 0); } else { - dbg(1, "spice_block_netlist(): loading: %s -> %s\n", - xctx->sym[i].name, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch")); - dbg(1, "spice_block_netlist(): current_dirname=%s\n", xctx->current_dirname); - load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch") ,0); + spice_stop? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch") ,0) : + load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch") ,0); } spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */ netlist_count++; @@ -377,10 +376,10 @@ void spice_netlist(FILE *fd, int spice_stop ) int i; char *type=NULL; - xctx->prep_net_structs = 0; - prepare_netlist_structs(1); - traverse_node_hash(); /* print all warnings about unconnected floatings etc */ if(!spice_stop) { + xctx->prep_net_structs = 0; + prepare_netlist_structs(1); + traverse_node_hash(); /* print all warnings about unconnected floatings etc */ for(i=0;iinstances;i++) /* print first ipin/opin defs ... */ { if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue; @@ -427,7 +426,7 @@ void spice_netlist(FILE *fd, int spice_stop ) } } } - if(!netlist_count) redraw_hilights(); /* draw_hilight_net(1); */ + if(!spice_stop && !netlist_count) redraw_hilights(); /* draw_hilight_net(1); */ my_free(952, &type); } diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c index 34432281..4ab259b2 100644 --- a/src/verilog_netlist.c +++ b/src/verilog_netlist.c @@ -383,7 +383,8 @@ void verilog_block_netlist(FILE *fd, int i) if((str_tmp = get_tok_value(xctx->sym[i].prop_ptr, "schematic",0 ))[0]) { my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename)); - load_schematic(1,filename, 0); + verilog_stop? load_schematic(0,filename, 0) : + load_schematic(1,filename, 0); } else { verilog_stop? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0) : load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0); @@ -506,17 +507,17 @@ void verilog_netlist(FILE *fd , int verilog_stop) int i; char *type=NULL; - xctx->prep_net_structs = 0; - prepare_netlist_structs(1); - /* set_modify(1); */ /* 20160302 prepare_netlist_structs could change schematic (wire node naming for example) */ - dbg(2, "verilog_netlist(): end prepare_netlist_structs\n"); - traverse_node_hash(); /* print all warnings about unconnected floatings etc */ + if(!verilog_stop) { + xctx->prep_net_structs = 0; + prepare_netlist_structs(1); + dbg(2, "verilog_netlist(): end prepare_netlist_structs\n"); + traverse_node_hash(); /* print all warnings about unconnected floatings etc */ + dbg(2, "verilog_netlist(): end traverse_node_hash\n"); + } - dbg(2, "verilog_netlist(): end traverse_node_hash\n"); - - fprintf(fd,"---- begin signal list\n"); + fprintf(fd,"---- begin signal list\n"); /* these are needed even if signal list empty */ if(!verilog_stop) print_verilog_signals(fd); - fprintf(fd,"---- end signal list\n"); + fprintf(fd,"---- end signal list\n"); /* these are needed even if signal list empty */ if(!verilog_stop) @@ -548,5 +549,5 @@ void verilog_netlist(FILE *fd , int verilog_stop) my_free(1084, &type); } dbg(1, "verilog_netlist(): end\n"); - if(!netlist_count) redraw_hilights(); /*draw_hilight_net(1); */ + if(!verilog_stop && !netlist_count) redraw_hilights(); /*draw_hilight_net(1); */ } diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c index 9552066f..0570cac0 100644 --- a/src/vhdl_netlist.c +++ b/src/vhdl_netlist.c @@ -432,7 +432,9 @@ void vhdl_block_netlist(FILE *fd, int i) my_strncpy(filename, abs_sym_path(str_tmp, ""), S(filename)); load_schematic(1,filename, 0); } else { - load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0); + /* this can not be done im VHDL as vhdl needs "arch_declaration" and "attributes" type instances */ + /* vhdl_stop ? load_schematic(0, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0) : */ + load_schematic(1, add_ext(abs_sym_path(xctx->sym[i].name, ""), ".sch"), 0); } dbg(1, "vhdl_block_netlist(): packages\n"); @@ -589,7 +591,6 @@ void vhdl_block_netlist(FILE *fd, int i) } } - if(xctx->schvhdlprop && xctx->schvhdlprop[0]) fprintf(fd, "%s\n", xctx->schvhdlprop); fprintf(fd, "end arch_%s ;\n\n", skip_dir(xctx->sym[i].name) ); /* skip_dir( xctx->sch[xctx->currsch]) ); */ if(split_files) { @@ -611,11 +612,12 @@ void vhdl_netlist(FILE *fd , int vhdl_stop) int i,l; char *type=NULL; - xctx->prep_net_structs = 0; - prepare_netlist_structs(1); /* set_modify(1); */ /* 20160302 prepare_netlist_structs could change schematic (wire node naming for example) */ - traverse_node_hash(); /* print all warnings about unconnected floatings etc */ - + if(!vhdl_stop) { + xctx->prep_net_structs = 0; + prepare_netlist_structs(1); + traverse_node_hash(); /* print all warnings about unconnected floatings etc */ + } dbg(1, "vhdl_netlist(): architecture declarations\n"); fprintf(fd, "//// begin user declarations\n"); @@ -689,6 +691,6 @@ void vhdl_netlist(FILE *fd , int vhdl_stop) } } dbg(1, "vhdl_netlist(): end\n"); - if(!netlist_count) redraw_hilights(); /* draw_hilight_net(1); */ + if(!vhdl_stop && !netlist_count) redraw_hilights(); /* draw_hilight_net(1); */ my_free(1097, &type); } diff --git a/xschem_library/logic/ram.sch b/xschem_library/logic/ram.sch index 5dfd3cc2..ee3d774a 100644 --- a/xschem_library/logic/ram.sch +++ b/xschem_library/logic/ram.sch @@ -1,4 +1,4 @@ -v {xschem version=2.9.6 file_version=1.1} +v {xschem version=2.9.9 file_version=1.2 } G { process(data, CEN, OEN) begin @@ -22,6 +22,7 @@ G { end if; end process; } +K {} V { integer i; reg [width-1:0] mem[0:(1<