From ae86b92fdacf8a92425bd6c6c6cbb8ca7615b7a1 Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Fri, 16 May 2025 23:43:34 +0200
Subject: [PATCH] simplify vectored capacitance attribute in ccap.sym used in
 sar_adc.sch

---
 xschem_library/ngspice_verilog_cosim/ccap.sym    | 4 ++--
 xschem_library/ngspice_verilog_cosim/sar_adc.sch | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/xschem_library/ngspice_verilog_cosim/ccap.sym b/xschem_library/ngspice_verilog_cosim/ccap.sym
index ac94fb3e..f7bf4bae 100644
--- a/xschem_library/ngspice_verilog_cosim/ccap.sym
+++ b/xschem_library/ngspice_verilog_cosim/ccap.sym
@@ -1,7 +1,7 @@
-v {xschem version=3.4.7RC file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.2}
 G {}
 K {type=subcircuit
-format="@name @pinlist @symname C = @C"
+format="@name @pinlist @symname C = ?1 @C"
 template="name=x1 C=1p"
 }
 V {}
diff --git a/xschem_library/ngspice_verilog_cosim/sar_adc.sch b/xschem_library/ngspice_verilog_cosim/sar_adc.sch
index ae45a55a..b01a9c49 100644
--- a/xschem_library/ngspice_verilog_cosim/sar_adc.sch
+++ b/xschem_library/ngspice_verilog_cosim/sar_adc.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.7RC file_version=1.2}
+v {xschem version=3.4.8RC file_version=1.2}
 G {}
 K {}
 V {}
@@ -83,6 +83,6 @@ C {lab_pin.sym} 930 -70 0 1 {name=p35 lab=COMP_A}
 C {noconn.sym} 170 -120 0 0 {name=l1}
 C {noconn.sym} 950 -180 3 0 {name=l2}
 C {noconn.sym} 860 -180 3 0 {name=l3}
-C {ccap.sym} 420 -360 0 0 {name=xb[6..1] C="?1 1p,'1p/2','1p/4','1p/8','1p/16','1p/32'"}
+C {ccap.sym} 420 -360 0 0 {name=xb[6..1] C="1p,'1p/2','1p/4','1p/8','1p/16','1p/32'"}
 C {lab_pin.sym} 360 -360 0 0 {name=p36 lab=VREF}
 C {lab_pin.sym} 360 -340 0 0 {name=p37 lab=D[5..0]}