From a725838850a9bdeb7e8498ec0f9f83457b9c9daa Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Wed, 28 Aug 2024 09:39:43 +0200 Subject: [PATCH] fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) --- .../tutorial_use_existing_subckt.html | 5 +- scconfig/src/default/db.c | 1 + src/draw.c | 5 +- src/token.c | 5 +- xschem_library/examples/test_lvs_ignore.sch | 11 +--- xschem_library/examples/test_short_option.sch | 53 ++++++++----------- xschem_library/generators/test_generators.sch | 12 +---- xschem_library/ngspice/and_ngspice.sym | 4 +- 8 files changed, 37 insertions(+), 59 deletions(-) diff --git a/doc/xschem_man/tutorial_use_existing_subckt.html b/doc/xschem_man/tutorial_use_existing_subckt.html index 47b71276..c821abbf 100644 --- a/doc/xschem_man/tutorial_use_existing_subckt.html +++ b/doc/xschem_man/tutorial_use_existing_subckt.html @@ -122,7 +122,7 @@ format="@name @pinlist @symname" 
 format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname"
-

+

In this case you specify the port order one by one explicitly. This can be used for spice primitive devices, spice subcircuits (like this example), VHDL and Verilog primitives. This method can NOT be used for VHDL and verilog subcircuits since for these you @@ -134,7 +134,7 @@ format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname" - +

  • Obtaining the pin ordering from the subcircuit definition specified via spice_sym_def

    @@ -183,7 +183,6 @@ x1 XZ XVCC XVSS XA XB XC symbol_include

    • - diff --git a/scconfig/src/default/db.c b/scconfig/src/default/db.c index fa2398a3..24ba9554 100644 --- a/scconfig/src/default/db.c +++ b/scconfig/src/default/db.c @@ -201,6 +201,7 @@ static char *readq(FILE *f, char *str, long strmax, int quote, int do_esc, int * } /* get the next chunk */ + *str = '\0'; fgets(str, strmax, f); } diff --git a/src/draw.c b/src/draw.c index 9a3445ef..3e00efc5 100644 --- a/src/draw.c +++ b/src/draw.c @@ -768,9 +768,10 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot, #endif my_strdup2(_ALLOC_ID_, &txtptr, translate(n, text.txt_ptr)); /* do another round of substitutions if some @var are found, but if not found leave @var as is */ - my_strdup2(_ALLOC_ID_, &txtptr, translate3(txtptr, 0, xctx->inst[n].prop_ptr, - xctx->sym[xctx->inst[n].ptr].templ, NULL )); dbg(1, "drawing string: str=%s prop=%s\n", txtptr, text.prop_ptr ? text.prop_ptr : "NULL"); + my_strdup2(_ALLOC_ID_, &txtptr, translate3(txtptr, 1, xctx->inst[n].prop_ptr, + xctx->sym[xctx->inst[n].ptr].templ, NULL )); + dbg(1, "after translate3: str=%s\n", txtptr); draw_string(textlayer, what, txtptr, (text.rot + ( (flip && (text.rot & 1) ) ? rot+2 : rot) ) & 0x3, flip^text.flip, text.hcenter, text.vcenter, diff --git a/src/token.c b/src/token.c index 655a018a..1f4d605a 100644 --- a/src/token.c +++ b/src/token.c @@ -4427,11 +4427,12 @@ const char *translate3(const char *s, int eat_escapes, const char *s1, const cha while(1) { c=*s++; + if(c=='\\') { escape=1; if(eat_escapes) c=*s++; } - else escape=0; + space=SPACE(c); if( state==TOK_BEGIN && (c=='@' || c=='%' ) && !escape ) state=TOK_TOKEN; /* 20161210 escape */ else if(state==TOK_TOKEN && token_pos > 1 && @@ -4441,6 +4442,8 @@ const char *translate3(const char *s, int eat_escapes, const char *s1, const cha ) ) state=TOK_SEP; + if( c != '\\' && escape ) escape = 0; + STR_ALLOC(&token, token_pos, &sizetok); if(state==TOK_TOKEN) token[token_pos++]=(char)c; else if(state==TOK_SEP) { diff --git a/xschem_library/examples/test_lvs_ignore.sch b/xschem_library/examples/test_lvs_ignore.sch index 9b823c19..df671383 100644 --- a/xschem_library/examples/test_lvs_ignore.sch +++ b/xschem_library/examples/test_lvs_ignore.sch @@ -26,8 +26,6 @@ S {} E {} L 7 980 -150 1160 -150 {} P 4 7 210 -290 210 -370 220 -370 210 -390 200 -370 210 -370 210 -290 {} -T {Title symbol has embedded TCL command -to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7} T {Set tcl variable lvs_ignore to: - 1 to short elements with lvs_ignore=short attribute set to disable elements with lvs_ignore=open attribute set @@ -76,14 +74,7 @@ lab=STARTUP} N 550 -520 700 -520 { lab=STARTUP} C {title.sym} 160 -30 0 0 {name=l1 -author="tcleval([ - if \{$show_pin_net_names == 0\} \{ - set lvs_ignore 0 - set show_pin_net_names 1 - xschem update_all_sym_bboxes - \} - return \{Stefan Schippers\} -])" +author="Stefan Schippers" } C {launcher.sym} 750 -90 0 0 {name=h1 descr="Toggle lvs_ignore variable and diff --git a/xschem_library/examples/test_short_option.sch b/xschem_library/examples/test_short_option.sch index e22f88cb..637d7cf5 100644 --- a/xschem_library/examples/test_short_option.sch +++ b/xschem_library/examples/test_short_option.sch @@ -27,8 +27,6 @@ E {} L 7 930 -250 1110 -250 {} P 4 7 330 -690 330 -610 320 -610 330 -590 340 -610 330 -610 330 -690 {} P 4 7 650 -600 600 -600 600 -610 580 -600 600 -590 600 -600 650 -600 {} -T {Title symbol has embedded TCL command -to enable show_pin_net_names.} 160 -120 0 0 0.4 0.4 { layer=6} T {Set tcl variable IGNORE to 1 or 0 to enable / disable / short some components} 50 -940 0 0 1 1 {} T {tcleval(IGNORE=$IGNORE)} 930 -290 0 0 0.6 0.6 {name=l1} @@ -47,41 +45,41 @@ depending on IGNORE} 1310 -540 0 0 0.4 0.4 { layer=1} N 130 -290 180 -290 { lab=NET_A} N 480 -290 530 -290 { -lab=NET_A} +lab=NET_B} N 180 -390 180 -290 { lab=NET_A} N 480 -390 480 -290 { -lab=NET_A} +lab=NET_B} N 180 -390 300 -390 { lab=NET_A} N 360 -390 480 -390 { -lab=NET_A} +lab=NET_B} N 160 -480 180 -480 { -lab=NET_D} +lab=NET_C} N 480 -480 530 -480 { -lab=#net1} +lab=NET_C} N 180 -580 180 -480 { -lab=NET_D} +lab=NET_C} N 480 -580 480 -480 { -lab=#net1} +lab=NET_C} N 180 -580 300 -580 { -lab=NET_D} +lab=NET_C} N 360 -580 480 -580 { -lab=#net1} +lab=NET_C} N 380 -480 480 -480 { -lab=#net1} +lab=NET_C} N 180 -480 300 -480 { -lab=NET_D} +lab=NET_C} N 380 -290 480 -290 { -lab=NET_A} +lab=NET_B} N 180 -290 300 -290 { lab=NET_A} N 610 -480 660 -480 { -lab=NET_E} +lab=#net1} N 660 -460 660 -400 { -lab=NET_E} +lab=#net1} N 660 -400 750 -400 { -lab=NET_E} +lab=#net1} N 660 -360 750 -360 { lab=NET_B} N 660 -360 660 -290 { @@ -91,21 +89,21 @@ lab=NET_B} N 980 -380 1020 -380 { lab=NET_E} N 660 -460 760 -460 { -lab=NET_E} +lab=#net1} N 820 -460 980 -460 { lab=NET_E} N 980 -460 980 -380 { lab=NET_E} N 660 -480 660 -460 { -lab=NET_E} +lab=#net1} N 120 -420 160 -420 { -lab=NET_D} +lab=NET_C} N 160 -480 160 -420 { -lab=NET_D} +lab=NET_C} N 1560 -590 1680 -590 { -lab=NET_B} +lab=#net2} N 120 -480 160 -480 { -lab=NET_D} +lab=NET_C} N 1760 -590 1820 -590 { lab=NET_F} N 1210 -590 1480 -590 { @@ -115,14 +113,7 @@ lab=NET_E} C {lab_pin.sym} 130 -290 0 0 {name=p3 sig_type=std_logic lab=NET_A} C {ipin.sym} 100 -190 0 0 { name=p4 lab=NET_D } C {title.sym} 160 -30 0 0 {name=l1 -author="tcleval([ - if \{$show_pin_net_names == 0\} \{ - set IGNORE 1 - set show_pin_net_names 1 - xschem update_all_sym_bboxes - \} - return \{Stefan Schippers\} -])" +author="Stefan Schippers" } C {short.sym} 330 -390 1 0 {name=x2 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])" diff --git a/xschem_library/generators/test_generators.sch b/xschem_library/generators/test_generators.sch index 60d90c6d..a0664179 100644 --- a/xschem_library/generators/test_generators.sch +++ b/xschem_library/generators/test_generators.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -38,8 +38,6 @@ it becomes a short} 720 -410 0 0 0.4 0.4 { layer=4} T {Tier generator (tier.tcl) if 'lab' matches VDD | VCC | VPP shows as supply node, else show as ground node} 240 -640 0 0 0.4 0.4 { layer=4} -T {Title symbol has embedded TCL command -to enable show_pin_net_names.} 160 -120 0 0 0.4 0.4 { layer=6} N 180 -300 180 -240 { lab=VSS} N 180 -480 180 -360 { @@ -94,11 +92,5 @@ tclcommand="edit_file [abs_sym_path res.tcl]" C {lab_show.sym} 460 -290 0 0 {name=l3} C {lab_show.sym} 570 -290 0 0 {name=l4} C {title.sym} 160 -30 0 0 {name=l5 -author="tcleval([ - if \{$show_pin_net_names == 0\} \{ - set show_pin_net_names 1 - xschem update_all_sym_bboxes - \} - return \{Stefan Schippers\} -])" +author="Stefan Schippers" } diff --git a/xschem_library/ngspice/and_ngspice.sym b/xschem_library/ngspice/and_ngspice.sym index 8eb1a8bb..dd6e69c3 100644 --- a/xschem_library/ngspice/and_ngspice.sym +++ b/xschem_library/ngspice/and_ngspice.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -39,4 +39,4 @@ A 4 5 0 30 270 180 {} T {@name} -16.25 -5 0 0 0.2 0.2 {} T {@#1:net_name} -22.5 -17.5 0 1 0.15 0.15 {layer=15} T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15} -T {@#3:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15} +T {@#2:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}