diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html index d75c05ef..d600ee07 100644 --- a/doc/xschem_man/developer_info.html +++ b/doc/xschem_man/developer_info.html @@ -782,6 +782,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
  • build_date time and date this file was built.
  • cadlayers number of layers
  • case_insensitive case_insensitive symbol matching
  • +
  • change_lw change line width when zooming
  • color_ps color postscript flag
  • constr_mv color postscript flag
  • current_dirname directory name of current design
  • @@ -807,6 +808,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
  • lastsel number of selected objects
  • line_width get line width
  • lines (xschem get lines n) number of lines on layer 'n'
  • +
  • min_lw minimum line width
  • modified schematic is in modified state (needs a save)
  • netlist_name netlist name if set. If 'fallback' given get default name
  • netlist_type get current netlist type (spice/vhdl/verilog/tedax)
  • @@ -1503,6 +1505,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"