diff --git a/xschem_library/pcb/hierarchical_tedax.sch b/xschem_library/pcb/hierarchical_tedax.sch
index a77bcd7d..925ce365 100644
--- a/xschem_library/pcb/hierarchical_tedax.sch
+++ b/xschem_library/pcb/hierarchical_tedax.sch
@@ -4,6 +4,7 @@ K {}
 V {}
 S {}
 E {}
+P 7 11 1280 -860 1280 -820 1180 -900 1280 -980 1280 -940 1500 -940 1500 -980 1600 -900 1500 -820 1500 -860 1280 -860 {fill=true}
 T {Example of hierarchical schematic
 to be netlisted in tEDAx format.
 Hierarchy is flattened and hierarchical 
@@ -12,6 +13,8 @@ avoid collisions.} 1330 -520 0 0 0.8 0.8 {}
 T {NOTE: circuit is doing nothing useful,
 just a collection of schematics to show
 hierarchical tEDAx netlisting} 1330 -220 0 0 0.8 0.8 {}
+T {Same design 
+repeated 2 times} 1180 -1140 0 0 1 1 {}
 N 540 -100 540 -80 {lab=VSS}
 N 540 -200 540 -160 {lab=VREF}
 N 540 -200 630 -200 {lab=VREF}
@@ -39,8 +42,8 @@ N 920 -240 920 -170 {lab=#net2}
 N 990 -220 990 -210 {lab=G}
 N 1020 -790 1070 -790 { lab=VOUT_PROTECTED1}
 N 70 -330 90 -330 { lab=#net3}
-N 2190 -840 2190 -790 { lab=VOUT_PROTECTED2}
-N 2140 -790 2190 -790 { lab=VOUT_PROTECTED2}
+N 2080 -920 2080 -870 { lab=VOUT_PROTECTED2}
+N 2030 -870 2080 -870 { lab=VOUT_PROTECTED2}
 N 390 -500 450 -500 { lab=VSS_ANALOG}
 C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
 C {lab_pin.sym} 70 -470 0 1 {name=p8 lab=VCC12}
@@ -100,10 +103,10 @@ C {lab_pin.sym} 70 -350 0 1 {name=p14 lab=VSSLOAD}
 C {noconn.sym} 90 -330 0 1 {name=l5}
 C {netlist_options.sym} 30 -260 0 0 {hiersep=.
 }
-C {voltage_protection.sch} 1130 -490 0 0 {name=xprot2}
-C {lab_pin.sym} 2190 -790 0 1 {name=p15 lab=VOUT_PROTECTED2}
-C {lab_pin.sym} 1300 -1200 0 0 {name=p16 lab=VCC12}
-C {diode.sym} 2190 -870 0 0 {name=D2 model=D1N914 area=1 device=D1N914 footprint=acy(300)}
-C {vdd.sym} 2190 -900 0 0 {name=l10 lab=VCC}
-C {lab_pin.sym} 1300 -1120 0 0 {name=p17 lab=VSS_ANALOG}
+C {voltage_protection.sym} 1880 -860 0 0 {name=xprot2}
+C {lab_pin.sym} 2080 -870 0 1 {name=p15 lab=VOUT_PROTECTED2}
+C {lab_pin.sym} 1730 -870 0 0 {name=p16 lab=VCC12}
+C {diode.sym} 2080 -950 0 0 {name=D2 model=D1N914 area=1 device=D1N914 footprint=acy(300)}
+C {vdd.sym} 2080 -980 0 0 {name=l10 lab=VCC}
+C {lab_pin.sym} 1730 -850 0 0 {name=p17 lab=VSS_ANALOG}
 C {lab_pin.sym} 70 -410 0 1 {name=p18 lab=VOUT_PROTECTED1}
diff --git a/xschem_library/pcb/voltage_protection.sym b/xschem_library/pcb/voltage_protection.sym
new file mode 100644
index 00000000..8cccf5a2
--- /dev/null
+++ b/xschem_library/pcb/voltage_protection.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -20 130 -20 {}
+L 4 -130 20 130 20 {}
+L 4 -130 -20 -130 20 {}
+L 4 130 -20 130 20 {}
+L 4 -150 -10 -130 -10 {}
+L 4 -150 10 -130 10 {}
+L 4 130 -10 150 -10 {}
+B 5 -152.5 -12.5 -147.5 -7.5 {name=VCC_UNREG dir=in name=p3 }
+B 5 -152.5 7.5 -147.5 12.5 {name=VSSA dir=in name=p1 }
+B 5 147.5 -12.5 152.5 -7.5 {name=VOUT dir=out name=p0 }
+T {@symname} -79 -46 0 0 0.3 0.3 {}
+T {@name} 135 -32 0 0 0.2 0.2 {}
+T {VCC_UNREG} -125 -14 0 0 0.2 0.2 {}
+T {VSSA} -125 6 0 0 0.2 0.2 {}
+T {VOUT} 125 -14 0 1 0.2 0.2 {}