diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html
index 0080e77f..a1b8d5d1 100644
--- a/doc/xschem_man/developer_info.html
+++ b/doc/xschem_man/developer_info.html
@@ -496,6 +496,12 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
+
+
+
+
+
+
@@ -516,7 +522,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
annotate_op [raw_file]
Annotate operating point data into current schematic.
use <schematic name>.raw or use supplied argument as raw file to open
- look for operating point data and annotate voltages/currents into schematic
+ look for operating point data and annotate voltages/currents
+ into schematic
arc
Start a GUI placement of an arc.
User should click 3 unaligned points to define the arc
@@ -526,8 +533,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
Start/end bounding box calculation: parameter is either 'begin' or 'end'
break_wires [remove]
Break wires at selected instance pins
- if '1' is given as 'remove' parameter broken wires that are all inside selected
- instances will be deleted
+ if '1' is given as 'remove' parameter broken wires that are
+ all inside selected instances will be deleted
build_colors
Rebuild color palette using values of tcl vars dim_value and dim_bg
callback winpath event mx my key button aux state
@@ -535,7 +542,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
case_insensitive 1|0
Set case insensitive symbol lookup. Use only on case insensitive filesystems
change_elem_order n
- set selected object (instance, wire, line, rect, ...) to position 'n' in its respective array
+ set selected object (instance, wire, line, rect, ...) to
+ position 'n' in its respective array
check_symbols
List all used symbols in current schematic and warn if some symbol is newer
check_unique_names [1|0]
@@ -559,12 +567,14 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
connected_nets [0|1|2|3]
Select nets/labels connected to currently selected instance
if '1' argument is given, stop at wire junctions
- if '2' argument is given select only wires directly attached to selected instance/net
+ if '2' argument is given select only wires directly
+ attached to selected instance/net
if '3' argument is given combine '1' and '2'
copy
Copy selection to clipboard
- copy_objects
- Start a GUI copy operation
+ copy_objects [deltax deltay [rot flip]]
+ if deltax and deltay (and optionally rot and flip) are given copy selection
+ to specified offset, otherwise start a GUI copy operation
count_items string separator quoting_chars
Debug command
create_plot_cmd
@@ -1347,6 +1357,7 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
+
diff --git a/src/save.c b/src/save.c
index 9c998c9d..3a4ac6fb 100644
--- a/src/save.c
+++ b/src/save.c
@@ -348,6 +348,36 @@ unsigned char *ascii85_encode(const unsigned char *data, const size_t input_leng
return encoded_data;
}
+/* Non-square 'r x c' matrix 'a' in-place transpose */
+void transpose_matrix(double *a, int r, int c)
+{
+ double t; /* holds element to be replaced, eventually becomes next element to move */
+ int size = r * c - 1;
+ int next; /* location of 't' to be moved */
+ int begin; /* holds start of cycle */
+ int i;
+ double tmp;
+ char *done = my_calloc(_ALLOC_ID_, r, c); /* hash to mark moved elements */
+
+ done[0] = done[size] = 1; /* first and last matrix elements are not moved. */
+ i = 1;
+ while (i < size) {
+ begin = i;
+ t = a[i];
+ do {
+ next = (i * r) % size;
+ SWAP(a[next], t, tmp);
+ dbg(1, "swap %g <--> %g\n", a[next], t);
+ done[i] = 1;
+ i = next;
+ } while (i != begin);
+ /* Get Next Move */
+ for (i = 1; i < size && done[i]; i++) ;
+ }
+ my_free(_ALLOC_ID_, &done);
+}
+
+
/* SPICE RAWFILE ROUTINES */
/* read the binary portion of a ngspice raw simulation file
* data layout in memory arranged to maximize cache locality
diff --git a/src/scheduler.c b/src/scheduler.c
index aa34acc5..4c965d4f 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -256,7 +256,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
/* annotate_op [raw_file]
* Annotate operating point data into current schematic.
* use .raw or use supplied argument as raw file to open
- * look for operating point data and annotate voltages/currents into schematic */
+ * look for operating point data and annotate voltages/currents
+ * into schematic */
else if(!strcmp(argv[1], "annotate_op"))
{
int i;
@@ -328,8 +329,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
/* break_wires [remove]
* Break wires at selected instance pins
- * if '1' is given as 'remove' parameter broken wires that are all inside selected
- * instances will be deleted */
+ * if '1' is given as 'remove' parameter broken wires that are
+ * all inside selected instances will be deleted */
else if(!strcmp(argv[1], "break_wires"))
{
int remove = 0;
@@ -380,7 +381,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
/* change_elem_order n
- * set selected object (instance, wire, line, rect, ...) to position 'n' in its respective array */
+ * set selected object (instance, wire, line, rect, ...) to
+ * position 'n' in its respective array */
else if(!strcmp(argv[1], "change_elem_order"))
{
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
@@ -517,7 +519,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
/* connected_nets [0|1|2|3]
* Select nets/labels connected to currently selected instance
* if '1' argument is given, stop at wire junctions
- * if '2' argument is given select only wires directly attached to selected instance/net
+ * if '2' argument is given select only wires directly
+ * attached to selected instance/net
* if '3' argument is given combine '1' and '2' */
else if(!strcmp(argv[1], "connected_nets"))
{
@@ -538,12 +541,26 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_ResetResult(interp);
}
- /* copy_objects
- * Start a GUI copy operation */
+ /* copy_objects [deltax deltay [rot flip]]
+ * if deltax and deltay (and optionally rot and flip) are given copy selection
+ * to specified offset, otherwise start a GUI copy operation */
else if(!strcmp(argv[1], "copy_objects"))
{
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
- copy_objects(START);
+ if(argc > 3) {
+ copy_objects(START);
+ xctx->deltax = atof(argv[2]);
+ xctx->deltay = atof(argv[3]);
+ if(argc > 4) {
+ xctx->move_rot = (short int)atoi(argv[4]);
+ }
+ if(argc > 5) {
+ xctx->move_flip = (short int)atoi(argv[5]);
+ }
+ copy_objects(END);
+ } else {
+ copy_objects(START);
+ }
Tcl_ResetResult(interp);
}
diff --git a/xschem_library/devices/ammeter.sym b/xschem_library/devices/ammeter.sym
index a9ec2c49..c70461fb 100644
--- a/xschem_library/devices/ammeter.sym
+++ b/xschem_library/devices/ammeter.sym
@@ -1,10 +1,11 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {type=ammeter
-format="@name @pinlist 0
-.save I( ?1 @name )"
-template="name=Vmeas"}
+format="tcleval([expr \{@savecurrent ? \\"@name @pinlist 0
+.save I( ?1 @name )\\" : \\"@name @pinlist 0\\"\}])"
+template="name=Vmeas savecurrent=true"
+}
V {}
S {}
E {}
diff --git a/xschem_library/devices/vsource.sym b/xschem_library/devices/vsource.sym
index 3b79b3cd..b9942c46 100644
--- a/xschem_library/devices/vsource.sym
+++ b/xschem_library/devices/vsource.sym
@@ -1,10 +1,11 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {type=vsource
-format="@name @pinlist @value
-.save I( ?1 @name )"
-template="name=V1 value=3"}
+format="tcleval([expr \{@savecurrent ? \\"@name @pinlist @value
+.save I( ?1 @name )\\" : \\"@name @pinlist @value \\"\}])"
+template="name=V1 value=3 savecurrent=false"
+}
V {}
S {}
E {}
diff --git a/xschem_library/examples/LCC_instances.sch b/xschem_library/examples/LCC_instances.sch
index aa1a455c..5d876e11 100644
--- a/xschem_library/examples/LCC_instances.sch
+++ b/xschem_library/examples/LCC_instances.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {type=subcircuit
@@ -82,7 +82,8 @@ N 700 -320 700 -240 {
lab=#net1}
N 700 -490 700 -380 {
lab=ZZ}
-C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3"}
+C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3"
+savecurrent=1}
C {lab_pin.sym} 50 -170 0 0 {name=p4 lab=A}
C {lab_pin.sym} 50 -110 0 0 {name=p5 lab=0}
C {code_shown.sym} 480 -280 0 0 {name=STIMULI
@@ -155,7 +156,8 @@ value="************************************************
"}
C {lab_pin.sym} 240 -190 0 0 {name=p6 lab=A}
C {lab_pin.sym} 430 -190 0 1 {name=p7 lab=ZZZ}
-C {vsource.sym} 50 -240 0 0 {name=V2 value=3}
+C {vsource.sym} 50 -240 0 0 {name=V2 value=3
+savecurrent=1}
C {lab_pin.sym} 50 -270 0 0 {name=p8 lab=VDD}
C {lab_pin.sym} 50 -210 0 0 {name=p9 lab=0}
C {res.sym} 410 -130 0 0 {name=R1
@@ -164,7 +166,8 @@ footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 410 -80 0 0 {name=p10 lab=HALF}
-C {vsource.sym} 50 -340 0 0 {name=V3 value=1.5}
+C {vsource.sym} 50 -340 0 0 {name=V3 value=1.5
+savecurrent=1}
C {lab_pin.sym} 50 -370 0 0 {name=p11 lab=HALF}
C {lab_pin.sym} 50 -310 0 0 {name=p12 lab=0}
C {lab_pin.sym} 120 -490 0 0 {name=p13 lab=A}
diff --git a/xschem_library/inst_sch_select/inst_sch_select.sch b/xschem_library/inst_sch_select/inst_sch_select.sch
index b95b688f..11785f3d 100644
--- a/xschem_library/inst_sch_select/inst_sch_select.sch
+++ b/xschem_library/inst_sch_select/inst_sch_select.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {}
@@ -242,13 +242,16 @@ C {code.sym} 0 -200 0 0 {name=MODELS only_toplevel=false value="* Beta Version r
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
"}
-C {vsource.sym} 700 -120 0 0 {name=V1 value=2}
+C {vsource.sym} 700 -120 0 0 {name=V1 value=2
+savecurrent=true}
C {lab_pin.sym} 700 -150 0 0 {name=p21 lab=VCC}
C {lab_pin.sym} 700 -90 0 0 {name=p10 lab=0}
-C {vsource.sym} 820 -120 0 0 {name=V2 value=1}
+C {vsource.sym} 820 -120 0 0 {name=V2 value=1
+savecurrent=true}
C {lab_pin.sym} 820 -150 0 0 {name=p11 lab=MINUS}
C {lab_pin.sym} 820 -90 0 0 {name=p12 lab=0}
-C {vsource.sym} 970 -120 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"}
+C {vsource.sym} 970 -120 0 0 {name=V3 value="pwl 0 0 10n 0 20n 2 30n 2 40n 0"
+savecurrent=true}
C {lab_pin.sym} 970 -150 0 0 {name=p13 lab=PLUS}
C {lab_pin.sym} 970 -90 0 0 {name=p14 lab=0}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
diff --git a/xschem_library/ngspice/inv_ngspice.sch b/xschem_library/ngspice/inv_ngspice.sch
index 14820883..7207833b 100644
--- a/xschem_library/ngspice/inv_ngspice.sch
+++ b/xschem_library/ngspice/inv_ngspice.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {}
@@ -27,5 +27,7 @@ C {lab_pin.sym} 130 -240 0 1 {name=l6 sig_type=std_logic lab=A1}
C {lab_pin.sym} 260 -240 0 0 {name=l7 sig_type=std_logic lab=Y1}
C {parax_cap.sym} 360 -460 0 0 {name=C1 gnd=0 value=8f m=1}
C {parax_cap.sym} 620 -460 0 0 {name=C2 gnd=0 value=8f m=1}
-C {vsource.sym} 290 -240 1 0 {name=V1 value=0}
-C {vsource.sym} 100 -240 1 0 {name=V2 value=0}
+C {vsource.sym} 290 -240 1 0 {name=V1 value=0
+savecurrent=1}
+C {vsource.sym} 100 -240 1 0 {name=V2 value=0
+savecurrent=1}
diff --git a/xschem_library/rom8k/rom8k.sch b/xschem_library/rom8k/rom8k.sch
index c669097a..1a7fee09 100644
--- a/xschem_library/rom8k/rom8k.sch
+++ b/xschem_library/rom8k/rom8k.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.1.0 file_version=1.2
+v {xschem version=3.4.4 file_version=1.2
}
G {}
K {}
@@ -196,13 +196,16 @@ C {lab_pin.sym} 410 -430 0 0 {name=p39 lab=LDYMS[15:0]}
C {lab_pin.sym} 410 -350 0 0 {name=p26 lab=vccsa}
C {lab_pin.sym} 410 -330 0 0 {name=p31 lab=vss}
C {lab_pin.sym} 410 -410 0 0 {name=p40 lab=LDOE}
-C {vsource.sym} 90 -920 0 0 {name=vsa value=0}
+C {vsource.sym} 90 -920 0 0 {name=vsa value=0
+savecurrent=1}
C {lab_pin.sym} 90 -950 0 0 {name=p44 lab=vcc}
C {lab_pin.sym} 90 -890 0 0 {name=p45 lab=vccsa}
-C {vsource.sym} 190 -820 0 0 {name=vdec value=0}
+C {vsource.sym} 190 -820 0 0 {name=vdec value=0
+savecurrent=1}
C {lab_pin.sym} 190 -850 0 0 {name=p48 lab=vcc}
C {lab_pin.sym} 190 -790 0 0 {name=p49 lab=vccdec}
-C {vsource.sym} 90 -820 0 0 {name=vl value=0}
+C {vsource.sym} 90 -820 0 0 {name=vl value=0
+savecurrent=1}
C {lab_pin.sym} 90 -850 0 0 {name=p50 lab=vcc}
C {lab_pin.sym} 90 -790 0 0 {name=p51 lab=vccl}
C {lab_pin.sym} 410 -390 0 0 {name=p5 lab=LDPRECH}