diff --git a/src/token.c b/src/token.c
index 460dd23d..f3f42210 100644
--- a/src/token.c
+++ b/src/token.c
@@ -3576,7 +3576,7 @@ static char *get_pin_attr(const char *token, int inst)
       if(rn) my_free(_ALLOC_ID_, &rn);
     }
 
-    if(!pin_attr_value ) my_strdup2(_ALLOC_ID_, &pin_attr_value, "--UNDEF--");
+    if(!pin_attr_value ) my_strdup2(_ALLOC_ID_, &pin_attr_value, "");
     my_strdup2(_ALLOC_ID_, &value, pin_attr_value);
     /* recognize slotted devices: instname = "U3:3", value = "a:b:c:d" --> value = "c" */
     if(pin_attr_value[0] && !strcmp(pin_attr, "pinnumber") ) {
diff --git a/xschem_library/ngspice/comp_65nm.sym b/xschem_library/ngspice/comp_65nm.sym
index 1cb97bf3..f5f86582 100644
--- a/xschem_library/ngspice/comp_65nm.sym
+++ b/xschem_library/ngspice/comp_65nm.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -41,3 +41,6 @@ T {@name} -10 -48.25 0 0 0.2 0.2 {}
 T {PLUS} -38.75 -30.25 0 0 0.2 0.2 {}
 T {OUT} 28.75 -5.25 0 1 0.2 0.2 {}
 T {MINUS} -38.75 18.5 0 0 0.2 0.2 {}
+T {@#PLUS:spice_get_voltage} -38.125 -17.34375 0 0 0.0625 0.0625 {layer=15}
+T {@#MINUS:spice_get_voltage} -38.125 13.90625 0 0 0.0625 0.0625 {layer=15}
+T {@#OUT:spice_get_voltage} 25.625 -8.59375 0 1 0.0625 0.0625 {layer=15}
diff --git a/xschem_library/ngspice/comp_ngspice.sym b/xschem_library/ngspice/comp_ngspice.sym
index 89d17867..fa2b7f01 100644
--- a/xschem_library/ngspice/comp_ngspice.sym
+++ b/xschem_library/ngspice/comp_ngspice.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -46,3 +46,6 @@ ROUT=@ROUT
 COUT=@COUT} 28 -46 0 0 0.2 0.2 {}
 T {OFFSET=@OFFSET} 8.75 32.5 0 0 0.2 0.2 {}
 T {AMPLITUDE=@AMPLITUDE} 8.75 21.25 0 0 0.2 0.2 {}
+T {@#PLUS:spice_get_voltage} -38.125 -17.34375 0 0 0.0625 0.0625 {layer=15}
+T {@#MINUS:spice_get_voltage} -38.125 13.90625 0 0 0.0625 0.0625 {layer=15}
+T {@#OUT:spice_get_voltage} 25.625 -8.59375 0 1 0.0625 0.0625 {layer=15}
diff --git a/xschem_library/ngspice/opamp_65nm.sym b/xschem_library/ngspice/opamp_65nm.sym
index 1cb97bf3..f5f86582 100644
--- a/xschem_library/ngspice/opamp_65nm.sym
+++ b/xschem_library/ngspice/opamp_65nm.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -41,3 +41,6 @@ T {@name} -10 -48.25 0 0 0.2 0.2 {}
 T {PLUS} -38.75 -30.25 0 0 0.2 0.2 {}
 T {OUT} 28.75 -5.25 0 1 0.2 0.2 {}
 T {MINUS} -38.75 18.5 0 0 0.2 0.2 {}
+T {@#PLUS:spice_get_voltage} -38.125 -17.34375 0 0 0.0625 0.0625 {layer=15}
+T {@#MINUS:spice_get_voltage} -38.125 13.90625 0 0 0.0625 0.0625 {layer=15}
+T {@#OUT:spice_get_voltage} 25.625 -8.59375 0 1 0.0625 0.0625 {layer=15}