From 870c3e44782202309fa8684dce1864a192e27e3e Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Tue, 24 Nov 2020 19:55:45 +0100 Subject: [PATCH] removed weird names (spaces etc) in hierarchical_tedax schematic objects. that was used for testing the hiertEDAx export. --- xschem_library/pcb/hierarchical_tedax.sch | 10 +++++----- xschem_library/pcb/lm358.sym | 2 +- xschem_library/pcb/reg.sch | 2 +- xschem_library/pcb/voltage_protection.sch | 18 +++++++++--------- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/xschem_library/pcb/hierarchical_tedax.sch b/xschem_library/pcb/hierarchical_tedax.sch index 1e53e36c..3bbc1241 100644 --- a/xschem_library/pcb/hierarchical_tedax.sch +++ b/xschem_library/pcb/hierarchical_tedax.sch @@ -19,9 +19,9 @@ N 540 -100 540 -80 {lab=VSS} N 540 -200 540 -160 {lab=VREF} N 540 -200 630 -200 {lab=VREF} N 540 -320 540 -290 {lab=VCC} -N 630 -380 630 -280 {lab=VSS\\ LOAD} -N 630 -380 1130 -380 {lab=VSS\\ LOAD} -N 1130 -380 1130 -360 {lab=VSS\\ LOAD} +N 630 -380 630 -280 {lab=VSSLOAD} +N 630 -380 1130 -380 {lab=VSSLOAD} +N 1130 -380 1130 -360 {lab=VSSLOAD} N 1130 -300 1130 -270 {lab=D} N 860 -120 880 -120 {lab=#net1} N 770 -120 800 -120 {lab=RST} @@ -37,7 +37,7 @@ N 390 -440 390 -420 {lab=VSS} N 310 -500 390 -500 { lab=VSS_ANALOG} N 310 -440 310 -420 {lab=VSS} N 540 -230 540 -200 {lab=VREF} -N 1130 -430 1130 -380 {lab=VSS\\ LOAD} +N 1130 -430 1130 -380 {lab=VSSLOAD} N 920 -240 920 -170 {lab=#net2} N 990 -220 990 -210 {lab=G} N 1020 -790 1070 -790 { lab=VOUT_PROTECTED1} @@ -48,7 +48,7 @@ N 390 -500 450 -500 { lab=VSS_ANALOG} C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"} C {lab_pin.sym} 70 -470 0 1 {name=p8 lab=VCC12} C {conn_8x1.sym} 50 -450 0 0 {name=C2} -C {lab_pin.sym} 1130 -400 0 0 {name=p1 lab=VSS\\ LOAD} +C {lab_pin.sym} 1130 -400 0 0 {name=p1 lab=VSSLOAD} C {lm358.sym} 710 -240 0 0 {name=U3:1 spiceprefix=X VCC=VCC diff --git a/xschem_library/pcb/lm358.sym b/xschem_library/pcb/lm358.sym index 07b59e62..5b6414e6 100644 --- a/xschem_library/pcb/lm358.sym +++ b/xschem_library/pcb/lm358.sym @@ -12,7 +12,7 @@ comptag @name @comptag" template="name=U1:1 model=LM358 device=LM358 -footprint=\\"SO(8)\\" +footprint=so(8) numslots=2 VCC=VCC VNN=VNN" diff --git a/xschem_library/pcb/reg.sch b/xschem_library/pcb/reg.sch index 4f7201c8..be5d4dc9 100644 --- a/xschem_library/pcb/reg.sch +++ b/xschem_library/pcb/reg.sch @@ -20,7 +20,7 @@ N 430 -110 590 -110 { lab=ANALOG_GND} N 430 -190 490 -190 { lab=VCC_IN} C {capa.sym} 590 -160 0 0 {name=C0 m=1 value=100u device="electrolitic capacitor"} C {7805.sym} 730 -190 0 0 {name=U0 -device=7805 +device=7805 footprint=TO220W spiceprefix=X url="https://www.sparkfun.com/datasheets/Components/LM7805.pdf"} C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"} diff --git a/xschem_library/pcb/voltage_protection.sch b/xschem_library/pcb/voltage_protection.sch index 6fd1da5f..832f8cf4 100644 --- a/xschem_library/pcb/voltage_protection.sch +++ b/xschem_library/pcb/voltage_protection.sch @@ -9,7 +9,7 @@ E {} B 2 170 -840 1010 -100 {dash=4} T {@name} 1010 -870 0 1 0.4 0.4 {} T {@symname} 170 -870 0 0 0.4 0.4 {} -N 920 -520 920 -390 {lab=VCC\\ FIVE} +N 920 -520 920 -390 {lab=VCC_FIVE} N 750 -360 880 -360 {lab=G} N 920 -300 1010 -300 {lab=VOUT} N 920 -170 920 -150 {lab=VSS} @@ -18,7 +18,7 @@ N 480 -310 480 -220 {lab=Z} N 480 -390 710 -390 {lab=B} N 480 -160 480 -130 {lab=VSSA} N 480 -430 480 -390 {lab=B} -N 750 -520 750 -420 {lab=VCC\\ FIVE} +N 750 -520 750 -420 {lab=VCC_FIVE} N 750 -260 750 -230 {lab=#net1} N 750 -170 750 -150 {lab=VSS} N 480 -390 480 -370 {lab=B} @@ -28,12 +28,12 @@ N 400 -160 400 -130 {lab=VSSA} N 400 -220 480 -220 {lab=Z} N 700 -320 800 -320 {lab=G} N 700 -260 800 -260 {lab=#net1} -N 480 -520 480 -490 { lab=VCC\\ FIVE} -N 480 -520 920 -520 { lab=VCC\\ FIVE} -N 920 -710 920 -520 { lab=VCC\\ FIVE} +N 480 -520 480 -490 { lab=VCC_FIVE} +N 480 -520 920 -520 { lab=VCC_FIVE} +N 920 -710 920 -520 { lab=VCC_FIVE} N 170 -710 310 -710 { lab=VCC_UNREG} N 170 -630 310 -630 { lab=VSSA} -N 820 -710 920 -710 { lab=VCC\\ FIVE} +N 820 -710 920 -710 { lab=VCC_FIVE} N 230 -740 230 -710 { lab=VCC_UNREG} C {conn_3x1.sym} 300 -360 0 0 {name=C1} C {opin.sym} 1010 -300 0 0 {name=p0 lab=VOUT} @@ -52,11 +52,11 @@ device=BZX5V1 footprint=acy(300) xxxspiceprefix="#D#"} C {lab_pin.sym} 480 -130 0 0 {name=l13 lab=VSSA} -C {res.sym} 480 -460 0 0 {name=Rdivider\\ upper m=1 value=4.7K footprint=1206 device=resistor} +C {res.sym} 480 -460 0 0 {name=Rdivider_upper m=1 value=4.7K footprint=1206 device=resistor} C {res.sym} 750 -200 0 0 {name=R5 m=1 value=470 footprint=1206 device=resistor} C {gnd.sym} 750 -150 0 0 {name=l16 lab=VSS} C {lab_wire.sym} 510 -390 0 0 {name=l0 lab=B} -C {res.sym} 480 -340 0 0 {name=Rdivider\\ lower m=1 value=510 footprint=1206 device=resistor} +C {res.sym} 480 -340 0 0 {name=Rdivider_lower m=1 value=510 footprint=1206 device=resistor} C {pmos.sym} 900 -360 0 0 {name=M2 model=IRLML6402 device=IRLML6402 @@ -81,6 +81,6 @@ C {lab_wire.sym} 480 -260 0 0 {name=l3 lab=Z} C {reg.sch} -120 -520 0 0 {name=x2} C {ipin.sym} 170 -710 0 0 {name=p3 lab=VCC_UNREG} C {ipin.sym} 170 -630 0 0 {name=p1 lab=VSSA} -C {lab_wire.sym} 690 -520 0 0 {name=l4 lab=VCC\\ FIVE} +C {lab_wire.sym} 690 -520 0 0 {name=l4 lab=VCC_FIVE} C {diode.sym} 230 -770 0 0 {name=D1 model=D1N914 area=1 device=D1N914 footprint=acy(300)} C {vdd.sym} 230 -800 0 0 {name=l5 lab=VCC}