diff --git a/xschem_library/logic/stimuli.test_ngspice b/xschem_library/logic/stimuli.test_ngspice
index 8ce0aba5..c7ea5f30 100644
--- a/xschem_library/logic/stimuli.test_ngspice
+++ b/xschem_library/logic/stimuli.test_ngspice
@@ -8,22 +8,24 @@ beginfile stimuli_test_ngspice.cir
 
 set A_A 0
 set B_A 0
-s 1000
+s 3000
 set A_A 1
 set B_A 0
-s 2000
+s 3000
 set A_A 1
 set B_A 1
-s 2000
+s 3000
 set A_A 0
 set B_A 1
-s 2000
+s 3000
 set A_A 0
 set B_A 0
-s 2000
+s 3000
 set A_A 0
 set B_A 1
-s 2000
+s 3000
+set A_A 0
+set B_A 0
 endfile
 
 
diff --git a/xschem_library/logic/test_ngspice.sch b/xschem_library/logic/test_ngspice.sch
index 00f8a937..634be04a 100644
--- a/xschem_library/logic/test_ngspice.sch
+++ b/xschem_library/logic/test_ngspice.sch
@@ -1,4 +1,5 @@
-v {xschem version=2.9.7 file_version=1.2}
+v {xschem version=3.1.0 file_version=1.2
+}
 G {process
 begin
 A<='0';
@@ -29,6 +30,7 @@ wait;
 end process;
 
 }
+K {}
 V {integer n = 0;
 
 initial begin
@@ -57,49 +59,61 @@ initial begin
   A=0;
 end
 }
-S {.model adc_buff adc_bridge(in_low = 0.3 in_high = 0.7)
-
-
-.model nand d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9
-+ input_load = 5e-15)
-
-.model nor d_nor(rise_delay = 0.7e-9 fall_delay = 0.2e-9
-+ input_load = 5e-15)
-
-.model dac_buff  dac_bridge(out_low = 0 out_high = 1.2 out_undef = 0.6
-+ input_load = 5.0e-15 t_rise = 0.5e-9
-+ t_fall = 0.2e-9)
-}
+S {}
 E {}
-B 21 490 -550 1060 -260 {}
-T {XSPICE DOMAIN} 600 -590 0 0 0.6 0.6 {}
-T {A --> D} 510 -320 0 0 0.6 0.6 {}
-T {D --> A} 950 -320 0 0 0.6 0.6 {}
-N 570 -380 700 -380 {lab=A}
-N 570 -340 700 -340 {lab=B}
-N 800 -360 980 -360 {lab=Y_NAND}
-N 1040 -360 1090 -360 {lab=Y_NAND_A}
-N 670 -520 700 -520 {lab=A}
-N 670 -480 700 -480 {lab=~B,~Y_NAND}
-N 800 -500 980 -500 {lab=Y_NOR}
-N 1040 -500 1090 -500 {lab=Y_NOR_A}
-N 460 -380 510 -380 {lab=A_A}
-N 460 -340 510 -340 {lab=B_A}
-N 480 -720 610 -720 {lab=A}
-N 480 -680 610 -680 {lab=B}
-N 710 -700 890 -700 {lab=Y_NAND4}
-N 950 -700 1000 -700 {lab=Y_NAND_A[4]}
+B 2 130 -1260 1450 -900 {flags=graph
+y1=0
+y2=2
+ypos1=0.0541696
+ypos2=1.13488
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=2.6e-05
+divx=5
+subdivx=1
+node="a_a
+b_a
+y_nand_a
+y_nor_a
+y_nand_ax4x"
+color="4 4 4 4 4"
+dataset=-1
+unitx=1
+logx=0
+logy=0
+digital=1}
+B 21 490 -760 1060 -360 {}
+T {XSPICE DOMAIN} 600 -800 0 0 0.6 0.6 {}
+T {A --> D} 510 -420 0 0 0.6 0.6 {}
+T {D --> A} 930 -420 0 0 0.6 0.6 {}
+N 570 -480 700 -480 {lab=A}
+N 570 -440 700 -440 {lab=B}
+N 800 -460 960 -460 {lab=Y_NAND}
+N 1020 -460 1090 -460 {lab=Y_NAND_A}
+N 670 -620 700 -620 {lab=A}
+N 670 -580 700 -580 {lab=~B,~Y_NAND}
+N 800 -600 960 -600 {lab=Y_NOR}
+N 1020 -600 1090 -600 {lab=Y_NOR_A}
+N 460 -480 510 -480 {lab=A_A}
+N 460 -440 510 -440 {lab=B_A}
+N 480 -730 610 -730 {lab=A}
+N 480 -690 610 -690 {lab=B}
+N 710 -710 960 -710 {lab=Y_NAND4}
+N 1020 -710 1090 -710 {lab=Y_NAND_A[4]}
 C {title.sym} 160 -30 0 0 {name=l2}
-C {verilog_timescale.sym} 30 -340 0 0 {name=s1 timestep="1ps" precision="1ps" }
-C {use.sym} 30 -440 0 0 {------------------------------------------------
+C {verilog_timescale.sym} 30 -440 0 0 {name=s1 timestep="1ps" precision="1ps" }
+C {use.sym} 30 -540 0 0 {------------------------------------------------
 library ieee;
         use ieee.std_logic_1164.all;
         use ieee.numeric_std.all;}
-C {lab_pin.sym} 460 -380 2 1 {name=p47 lab=A_A verilog_type=reg}
-C {lab_pin.sym} 460 -340 2 1 {name=p48 lab=B_A verilog_type=reg}
-C {adc_bridge.sym} 540 -380 0 0 {name=a1 delay=1}
-C {adc_bridge.sym} 540 -340 0 0 {name=a2 delay=1}
-C {code_shown.sym} 30 -260 0 0 {name=STIMULI
+C {lab_pin.sym} 460 -480 2 1 {name=p47 lab=A_A verilog_type=reg}
+C {lab_pin.sym} 460 -440 2 1 {name=p48 lab=B_A verilog_type=reg}
+C {adc_bridge.sym} 540 -480 0 0 {name=a1 delay=1}
+C {adc_bridge.sym} 540 -440 0 0 {name=a2 delay=1
+device_model=".model adc_buff adc_bridge(in_low = 0.3 in_high = 0.7)"}
+C {code_shown.sym} 30 -330 0 0 {name=STIMULI
 place=end
 vhdl_ignore=true
 verilog_ignore=true
@@ -112,29 +126,41 @@ value="
 .include stimuli_test_ngspice.cir
 
 .control
+save all
 tran 100n 26u
 eprvcd A B Y_NAND  > zzzz.vcd
+write test_ngspice.raw
 .endc
 "}
-C {lab_wire.sym} 670 -380 0 1 {name=l3 lab=A}
-C {lab_wire.sym} 670 -340 0 1 {name=l4 lab=B}
-C {lab_wire.sym} 830 -360 0 1 {name=l5 lab=Y_NAND}
-C {nd2.sym} 740 -360 0 0 {name=a3 delay="120 ps" del=120}
-C {dac_bridge.sym} 1010 -360 0 0 {name=a4 }
-C {lab_pin.sym} 1090 -360 2 0 {name=p1 lab=Y_NAND_A}
-C {netlist_options.sym} 30 -510 0 0 {bus_replacement_char="xx"}
-C {lab_pin.sym} 670 -520 2 1 {name=p13 lab=A}
-C {lab_pin.sym} 670 -480 2 1 {name=p14 lab=~B,~Y_NAND}
-C {lab_wire.sym} 870 -500 0 1 {name=l15 lab=Y_NOR}
-C {dac_bridge.sym} 1010 -500 0 0 {name=a6 }
-C {lab_pin.sym} 1090 -500 2 0 {name=p16 lab=Y_NOR_A}
-C {nr2.sym} 740 -500 0 0 {name=a5 delay="200 ps" del=200}
-C {lab_wire.sym} 580 -720 0 1 {name=l1 lab=A}
-C {lab_wire.sym} 580 -680 0 1 {name=l6 lab=B}
-C {lab_wire.sym} 740 -700 0 1 {name=l7 lab=Y_NAND4}
-C {nd2.sym} 650 -700 0 0 {name=a7 delay="120 ps" del=120}
-C {dac_bridge.sym} 920 -700 0 0 {name=a8 }
-C {lab_pin.sym} 1000 -700 2 0 {name=p2 lab=Y_NAND_A[4]}
-C {assign.sym} 1280 -470 0 0 {name=v1 delay=1}
-C {lab_pin.sym} 1250 -470 2 1 {name=p3 lab=Y_NOR_A}
-C {lab_pin.sym} 1310 -470 2 0 {name=p4 lab=Y_NOR[3]}
+C {lab_wire.sym} 670 -480 0 1 {name=l3 lab=A}
+C {lab_wire.sym} 670 -440 0 1 {name=l4 lab=B}
+C {lab_wire.sym} 830 -460 0 1 {name=l5 lab=Y_NAND}
+C {nd2.sym} 740 -460 0 0 {name=a3 delay="120 ps" del=120}
+C {dac_bridge.sym} 990 -460 0 0 {name=a4 
+device_model=".model dac_buff  dac_bridge(out_low = 0 out_high = 1.2 out_undef = 0.6
++ input_load = 5.0e-15 t_rise = 0.5e-9
++ t_fall = 0.2e-9)"}
+C {lab_pin.sym} 1090 -460 2 0 {name=p1 lab=Y_NAND_A}
+C {netlist_options.sym} 30 -610 0 0 {bus_replacement_char="xx"}
+C {lab_pin.sym} 670 -620 2 1 {name=p13 lab=A}
+C {lab_pin.sym} 670 -580 2 1 {name=p14 lab=~B,~Y_NAND}
+C {lab_wire.sym} 870 -600 0 1 {name=l15 lab=Y_NOR}
+C {dac_bridge.sym} 990 -600 0 0 {name=a6 }
+C {lab_pin.sym} 1090 -600 2 0 {name=p16 lab=Y_NOR_A}
+C {nr2.sym} 740 -600 0 0 {name=a5 delay="200 ps" del=200
+device_model=".model nor d_nor(rise_delay = 0.7e-9 fall_delay = 0.2e-9
++ input_load = 5e-15)"
+}
+C {lab_wire.sym} 580 -730 0 1 {name=l1 lab=A}
+C {lab_wire.sym} 580 -690 0 1 {name=l6 lab=B}
+C {lab_wire.sym} 740 -710 0 1 {name=l7 lab=Y_NAND4}
+C {nd2.sym} 650 -710 0 0 {name=a7 delay="120 ps" del=120
+
+device_model=".model nand d_nand(rise_delay = 0.5e-9 fall_delay = 0.3e-9
++ input_load = 5e-15)"}
+C {dac_bridge.sym} 990 -710 0 0 {name=a8 }
+C {lab_pin.sym} 1090 -710 2 0 {name=p2 lab=Y_NAND_A[4]}
+C {launcher.sym} 530 -870 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_ngspice.raw tran"
+}