From 7ad930e7f087d81fec10a69d82def7e8f2c45910 Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Wed, 10 May 2023 03:13:13 +0200
Subject: [PATCH] istances with *_ignore=true attribute will be drawn greyed
 out in schematics in the corresponding netlisting mode; command in Properties
 menu to toggle this attribute on selected instances

---
 doc/xschem_man/developer_info.html         |  7 +--
 doc/xschem_man/symbol_property_syntax.html |  6 +++
 src/draw.c                                 | 54 +++++++++++++++++++++-
 src/scheduler.c                            | 32 ++++++++++++-
 src/spice_netlist.c                        |  2 +-
 src/tedax_netlist.c                        |  2 +-
 src/verilog_netlist.c                      |  4 +-
 src/xschem.h                               |  3 +-
 src/xschem.tcl                             |  2 +
 9 files changed, 101 insertions(+), 11 deletions(-)

diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html
index 316f6fa0..582553a5 100644
--- a/doc/xschem_man/developer_info.html
+++ b/doc/xschem_man/developer_info.html
@@ -1119,11 +1119,13 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
    testmode </pre>
    <li><kbd>       toggle_colorscheme</kbd></li><pre>
    Toggle dark/light colorscheme </pre>
+   <li><kbd>       toggle_ignore</kbd></li><pre>
+   toggle *_ignore=true attribute on selected instances
+   * = {spice,verilog,vhdl,tedax} depending on current netlist mode </pre>
    <li><kbd>       translate n str</kbd></li><pre>
    Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes
      Example: xschem translate vref {the voltage is @value}
-     the voltage is 1.8 
-</pre>
+     the voltage is 1.8 </pre>
    <li><kbd>       trim_wires</kbd></li><pre>
    Remove operlapping wires, join lines, trim wires at intersections </pre>
    <li><kbd>       undo</kbd></li><pre>
@@ -1170,7 +1172,6 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
    Zoom to selection </pre>
 
 
-
  </ul>
 
   <!-- TCL global variables -->
diff --git a/doc/xschem_man/symbol_property_syntax.html b/doc/xschem_man/symbol_property_syntax.html
index 88716fdb..0159a467 100644
--- a/doc/xschem_man/symbol_property_syntax.html
+++ b/doc/xschem_man/symbol_property_syntax.html
@@ -502,6 +502,12 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
    <kbd>opamp_65nm_empty.sch</kbd>, ... and define some user accessible method in hierarchy_config procedure
    to select one of these 'switch' schematics.
   </p>
+  <li><kbd>symbol_ignore</kbd></li>
+  <p>
+   This attribute can be attached to symbol elements, like lines, rectangles, polygons, arcs, texts, 
+   wires and instances (in case of lcc symbols). If set to true (<kbd>symbol_ignore=true</kbd>)
+   the corresponding element will not be displayed when the symbol is instantiated.
+  </p>
  </ul>
  <h3>PREDEFINED SYMBOL VALUES</h3>
  <ul>
diff --git a/src/draw.c b/src/draw.c
index 33d3d866..ec6c3c66 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -419,7 +419,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
         double xoffset, double yoffset)
                             /* draws current layer only, should be called within  */
 {                           /* a "for(i=0;i<cadlayers; ++i)" loop */
-  int k, j, textlayer, hide = 0;
+  int k, j, textlayer, hide = 0, disabled = 0;
   double x0,y0,x1,y1,x2,y2;
   double *x, *y; /* polygon point arrays */
   short flip;
@@ -436,6 +436,55 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
   #endif
 
   if(xctx->inst[n].ptr == -1) return;
+  if(  layer == 0) { 
+    if(
+        (
+          xctx->netlist_type == CAD_SPICE_NETLIST &&
+          (
+            !strcmp(get_tok_value(xctx->inst[n].prop_ptr, "spice_ignore", 0), "true") ||
+            !strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "spice_ignore", 0), "true")
+          )
+        ) || 
+
+        (
+          xctx->netlist_type == CAD_VERILOG_NETLIST &&
+          (
+            !strcmp(get_tok_value(xctx->inst[n].prop_ptr, "verilog_ignore", 0), "true") ||
+            !strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "verilog_ignore", 0), "true")
+          )
+        ) ||
+
+        (
+          xctx->netlist_type == CAD_VHDL_NETLIST &&
+          (
+            !strcmp(get_tok_value(xctx->inst[n].prop_ptr, "vhdl_ignore", 0), "true") ||
+            !strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "vhdl_ignore", 0), "true")
+          )
+        ) ||
+
+        (
+          xctx->netlist_type == CAD_TEDAX_NETLIST &&
+          (
+            !strcmp(get_tok_value(xctx->inst[n].prop_ptr, "tedax_ignore", 0), "true") ||
+            !strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "tedax_ignore", 0), "true")
+          )
+        )
+
+      ) {
+       xctx->inst[n].flags |= 16; /* *_ignore=true */
+    } else {
+       xctx->inst[n].flags &= ~16;
+    }
+  }
+  if(xctx->inst[n].flags & 16) {
+     char *type = xctx->sym[xctx->inst[n].ptr].type;
+     if( strcmp(type, "launcher") && strcmp(type, "logo") && strcmp(type, "probe") &&
+         strcmp(type, "raw_data_show") ) {
+       c = GRIDLAYER;
+       what = NOW;
+       disabled = 1;
+     }
+  }
   if( (layer != PINLAYER && !xctx->enable_layer[layer]) ) return;
   if(!has_x) return;
   if( (xctx->inst[n].flags & HIDE_INST) ||
@@ -568,7 +617,8 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
       ROTATION(rot, flip, 0.0,0.0,text.x0,text.y0,x1,y1);
       textlayer = c;
       /* do not allow custom text color on hilighted instances */
-      if( xctx->inst[n].color == -10000) {
+      if(disabled) textlayer = GRIDLAYER;
+      else if( xctx->inst[n].color == -10000) {
         textlayer = symptr->text[j].layer;
         if(xctx->only_probes) textlayer = GRIDLAYER;
         else if(textlayer < 0 || textlayer >= cadlayers) textlayer = c;
diff --git a/src/scheduler.c b/src/scheduler.c
index 04de26e2..79c0d24c 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -3675,11 +3675,41 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
       Tcl_ResetResult(interp);
     }
 
+    /* toggle_ignore
+     *   toggle *_ignore=true attribute on selected instances
+     *   * = {spice,verilog,vhdl,tedax} depending on current netlist mode */
+    else if(!strcmp(argv[1], "toggle_ignore"))
+    {
+      int i, n, first = 1, remove = 0;
+      char *attr;
+      if(xctx->netlist_type == CAD_VERILOG_NETLIST) attr="verilog_ignore";
+      else if(xctx->netlist_type == CAD_VHDL_NETLIST) attr="vhdl_ignore";
+      else if(xctx->netlist_type == CAD_TEDAX_NETLIST) attr="tedax_ignore";
+      else  attr="spice_ignore";
+      rebuild_selected_array();
+      for(n=0; n < xctx->lastsel; ++n) {
+        if(xctx->sel_array[n].type == ELEMENT) {
+          i = xctx->sel_array[n].n;
+          if(first && !strcmp(get_tok_value(xctx->inst[i].prop_ptr, attr, 0), "true")) {
+            first = 0;
+            remove = 1;
+          }
+          if(remove) {
+            my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, NULL));
+          } else {
+            my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, "true"));
+          }
+          set_modify(1);
+        }
+      }
+      draw();
+      Tcl_ResetResult(interp);
+    }
+
     /* translate n str
      *   Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes
      *     Example: xschem translate vref {the voltage is @value}
      *     the voltage is 1.8 */
-
     else if(!strcmp(argv[1], "translate") )
     {
       if(argc>3) {
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index f8d5c9e4..a3f4eef8 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -208,7 +208,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
        } else {
          const char *m;
          if(print_spice_element(fd, i)) {
-           int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+           int_hash_lookup(&used_symbols, get_sym_name(i, 9999, 1), 1, XINSERT); /* symbol is used */
            fprintf(fd, "**** end_element\n");
          }
          /* hash device_model attribute if any */
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index e4a967fe..6975fe00 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -66,7 +66,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
          fprintf(fd,"#**** end user architecture code\n");
        } else {
          print_tedax_element(fd, i) ;  /* this is the element line  */
-         int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+         int_hash_lookup(&used_symbols, get_sym_name(i, 9999, 1), 1, XINSERT); /* symbol is used */
 
        }
      }
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index 62f59edc..ae9ca2b2 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -63,12 +63,12 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
      {
       if(xctx->inst[i].sel==SELECTED) {
         print_verilog_element(fd, i) ;
-        int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+        int_hash_lookup(&used_symbols, get_sym_name(i, 9999, 1), 1, XINSERT); /* symbol is used */
       }
      }
      else {
        print_verilog_element(fd, i) ;  /* this is the element line  */
-       int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+       int_hash_lookup(&used_symbols, get_sym_name(i, 9999, 1), 1, XINSERT); /* symbol is used */
      }
     }
    }
diff --git a/src/xschem.h b/src/xschem.h
index 2577b542..92da3b03 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -546,7 +546,8 @@ typedef struct
                 * bit 1: flag for different textlayer for pin/labels,
                 *        1: ordinary symbol, 0: label/pin/show 
                 * bit 2: highlight if connected net/label is highlighted
-                * bit 3: hidden instance, show only bounding box (hide=true attribute)*/
+                * bit 3: hidden instance, show only bounding box (hide=true attribute)
+                * bit 4: disabled instance (*_ignore=true), will draw in grey */
   char *prop_ptr;
   char **node;
   char *lab;      /*  lab attribute if any (pin/label) */
diff --git a/src/xschem.tcl b/src/xschem.tcl
index b437ead4..3205ae77 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -5999,6 +5999,8 @@ proc build_widgets { {topwin {} } } {
   $topwin.menubar.prop.menu add command -label "Edit" -command "xschem edit_prop" -accelerator Q
   $topwin.menubar.prop.menu add command -label "Edit with editor" -command "xschem edit_vi_prop" -accelerator Shift+Q
   $topwin.menubar.prop.menu add command -label "View" -command "xschem view_prop" -accelerator Ctrl+Shift+Q
+  $topwin.menubar.prop.menu add command -label "Toggle *_ignore attribute on selected instances" \
+     -command "xschem toggle_ignore"
   $topwin.menubar.prop.menu add command -label "Edit Header/License text" \
      -command { update_schematic_header } -accelerator Shift+B
   $topwin.menubar.prop.menu add command -background red -label "Edit file (danger!)" \