From 72363cf2d4295e2ed7dd7b295197bc4b56f79ea1 Mon Sep 17 00:00:00 2001
From: Stefan Schippers <stefan.schippers@gmail.com>
Date: Mon, 5 Oct 2020 04:18:31 +0200
Subject: [PATCH] better wire bbox calculation in find_inst_to_be_redrawn()

---
 src/actions.c                        | 2 +-
 src/move.c                           | 2 --
 xschem_library/examples/cmos_inv.sch | 4 ++--
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/actions.c b/src/actions.c
index bacd922e..15a09b15 100644
--- a/src/actions.c
+++ b/src/actions.c
@@ -1672,6 +1672,7 @@ void new_wire(int what, double mx_snap, double my_snap)
        }
        prepared_hash_wires = 0;
        prepared_hilight_structs = 0;
+       update_conn_cues(1,1);
        if(show_pin_net_names) {
          prepare_netlist_structs(0);
          find_inst_hash_clear();
@@ -1718,7 +1719,6 @@ void new_wire(int what, double mx_snap, double my_snap)
    }
    if( what & END) {
      ui_state &= ~STARTWIRE;
-     update_conn_cues(1,1);
    }
    if( (what & RUBBER)  ) {
      if(manhattan_lines==1) {
diff --git a/src/move.c b/src/move.c
index e213191c..d429e852 100644
--- a/src/move.c
+++ b/src/move.c
@@ -470,7 +470,6 @@ void find_inst_to_be_redrawn(const char *node)
       }
     }
   }
-  /* 
   for(i=0;i < lastwire; i++) {
     if(node && wire[i].node && !strcmp(wire[i].node, node )) {
       if(wire[i].bus){
@@ -488,7 +487,6 @@ void find_inst_to_be_redrawn(const char *node)
       }
     }
   }
-  */
 }
 
 void copy_objects(int what)
diff --git a/xschem_library/examples/cmos_inv.sch b/xschem_library/examples/cmos_inv.sch
index 06fd9c25..15b3b5c4 100644
--- a/xschem_library/examples/cmos_inv.sch
+++ b/xschem_library/examples/cmos_inv.sch
@@ -17,8 +17,8 @@ N 60 -230 100 -230 {lab=A}
 N 140 -230 190 -230 {lab=Z}
 N 140 -340 140 -320 {lab=VDD}
 N 140 -140 140 -120 {lab=0}
-C {nmos4.sym} 120 -170 0 0 {name=M1 model=n w=WN l=LLN m=1 net_name=true}
-C {pmos4.sym} 120 -290 0 0 {name=M2 model=p w=WP l=LLP m=1 net_name=true}
+C {nmos4.sym} 120 -170 0 0 {name=M1 model=n w=WN l=LLN m=1}
+C {pmos4.sym} 120 -290 0 0 {name=M2 model=p w=WP l=LLP m=1}
 C {vdd.sym} 140 -340 0 0 {name=l1 lab=VDD}
 C {lab_pin.sym} 140 -120 0 0 {name=l2 sig_type=std_logic lab=0}
 C {ipin.sym} 60 -230 0 0 {name=p1 lab=A}