From 64e29f6a8b8f0d8d1a88bc86bcbaf0c18a945807 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Sat, 22 Feb 2025 01:38:38 +0100 Subject: [PATCH] doc updates --- doc/xschem_man/developer_info.html | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html index 0cc1b8b6..44a2b51b 100644 --- a/doc/xschem_man/developer_info.html +++ b/doc/xschem_man/developer_info.html @@ -1634,6 +1634,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns" Unhighlight selected nets/pins
  • unselect_all [draw]
  •     Unselect everything. If draw is given and set to '0' no drawing is done 
    +
  • unselect_attached_floaters
  • +   Unselect objects (not symbol instances) attached to some instance with a 
    +   non empty name=... attribute 
  • update_all_sym_bboxes
  •     Update all symbol bounding boxes 
  • update_op