diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html
index 0cc1b8b6..44a2b51b 100644
--- a/doc/xschem_man/developer_info.html
+++ b/doc/xschem_man/developer_info.html
@@ -1634,6 +1634,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
    Unhighlight selected nets/pins </pre>
    <li><kbd>       unselect_all [draw]</kbd></li><pre>
    Unselect everything. If draw is given and set to '0' no drawing is done </pre>
+   <li><kbd>       unselect_attached_floaters</kbd></li><pre>
+   Unselect objects (not symbol instances) attached to some instance with a 
+   non empty name=... attribute </pre>
    <li><kbd>       update_all_sym_bboxes</kbd></li><pre>
    Update all symbol bounding boxes </pre>
    <li><kbd>       update_op</kbd></li><pre>