From 5aeb94c3c38c5934916e772cb90581950b41b8d2 Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Wed, 27 Aug 2025 00:02:48 +0200
Subject: [PATCH] doc updates (propag and goto symbol pin attributes)

---
 doc/xschem_man/symbol_property_syntax.html | 15 ++++++---------
 xschem_library/xschem_simulator/dev-1.sym  |  5 +++--
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/doc/xschem_man/symbol_property_syntax.html b/doc/xschem_man/symbol_property_syntax.html
index 3eb278f5..3fa816f7 100644
--- a/doc/xschem_man/symbol_property_syntax.html
+++ b/doc/xschem_man/symbol_property_syntax.html
@@ -394,20 +394,20 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
   If this attribute is defined in symbol it will be used as a prefix to the symbol name and subcircuit
   expansion in verilog netlists.
   </p>
-  <li><kbd>dir</kbd></li>
+  <li><kbd>dir</kbd> (pin attribute)</li>
   <p> 
    Defines the direction of a symbol pin. Allowed values are <kbd>in</kbd>, <kbd>out</kbd>, <kbd>inout</kbd>.
   </p>
    <img src="symbol_property_syntax2.png">
   <a id="pinnumber">
-  <li><kbd>pinnumber</kbd></li>
+  <li><kbd>pinnumber</kbd> (pin attribute)</li>
   </a>
   <p> 
    For packaged devices (tEDAx netlists) : indicate the position of the pin on the package.
    This can be overriden at instance level by attributes <kbd>pinnumber(name)</kbd> set in the instance
    for tEDAx netlists.
    <br><br>
-  <li><kbd>sim_pinnumber</kbd></li>
+  <li><kbd>sim_pinnumber</kbd> (pin attribute)</li>
    For VHDL, SPICE, Verilog, Spectre netlists: define the ordering of symbol ports in netlist.
    If all symbol pins have a sim_pinnumber attribute this symbol will be netlisted 
    (in all netlist formats) with pins sorted in ascending order according to sim_pinnumber value.
@@ -432,16 +432,13 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
   the other pin ordering.
   </p>
 
-
-
-
-  <li><kbd>propag=n</kbd></li>
+  <li><kbd>propag=n[,m,...]</kbd> (pin attribute)</li>
   <p>
   This attribute instructs xschem to do a 'propagate highlight' from the pin with this attribute to the
   pin <kbd>n</kbd>. The number 'n' refers to the pin sequence number (do a <kbd>shift-S</kbd> after
   selecting destination pin to know this information).
   </p>
-  <li><kbd>goto=n[,m,...]</kbd></li>
+  <li><kbd>goto=n[,m,...]</kbd> (pin attribute)</li>
   <p>
   This attribute is used in the xschem embedded digital simulation engine: propagate logic simulation
   to the output pins <kbd>n,[m,...]</kbd>. The logic function is defined via the 'function<kbd>n</kbd>'
@@ -450,7 +447,7 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
   </p>
    <img src="symbol_property_syntax4.png">
 
-  <li><kbd>clock=n</kbd></li>
+  <li><kbd>clock=n</kbd> (pin attribute)</li>
   <p>
    A <kbd>clock</kbd> attribute defined on input pins add some information on the pin function as follows:
    <ul>
diff --git a/xschem_library/xschem_simulator/dev-1.sym b/xschem_library/xschem_simulator/dev-1.sym
index 9e39ee09..5499f731 100644
--- a/xschem_library/xschem_simulator/dev-1.sym
+++ b/xschem_library/xschem_simulator/dev-1.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -27,6 +27,7 @@ template="name=s1"
 }
 V {}
 S {}
+F {}
 E {}
 L 4 10 -10 30 -10 {}
 L 4 -30 0 -10 0 {}
@@ -35,7 +36,7 @@ L 4 10 10 30 10 {}
 L 4 -10 0 10 0 {}
 L 4 -20 -5 -10 0 {}
 L 4 -20 5 -10 0 {}
-B 5 -32.5 -2.5 -27.5 2.5 {name=t0 dir=inout goto=1,2}
+B 5 -32.5 -2.5 -27.5 2.5 {name=t0 dir=inout goto=1,2 propag=1,2}
 B 5 27.5 7.5 32.5 12.5 {name=t1 dir=inout  }
 B 5 27.5 -12.5 32.5 -7.5 {name=t2 dir=inout  }
 B 5 -2.5 -42.5 2.5 -37.5 {name=g dir=inout goto=1,2}