diff --git a/doc/xschem_man/component_property_syntax.html b/doc/xschem_man/component_property_syntax.html
index 7120c821..9c2dafd2 100644
--- a/doc/xschem_man/component_property_syntax.html
+++ b/doc/xschem_man/component_property_syntax.html
@@ -250,6 +250,10 @@ name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
   <p> This will override at instance level the value of attribute <kbd>pinnumber</kbd> of <kbd>index</kbd>th pin of the symbol.
       This is mainly used for tedax, where by back annotation a connection to a symbol must be changed.
       This notation is faster since xschem does not have to find a pin by string matching.</p>
+
+  <li><kbd>pin_attr(name|index)</kbd></li>
+  <p> This is a general mechanism where at instance level a pin attribute may be overridden for netlisting. Example:<br>
+      <kbd> sig_type(OUT)=bit_vector</kbd> (set VHDL type of pin OUT to bit_vector).</p>
  </ul><br>
 
  <h3>TCL ATTRIBUTE SUBSTITUTION</h3>
diff --git a/doc/xschem_man/symbol_property_syntax.html b/doc/xschem_man/symbol_property_syntax.html
index 9c5b1e87..1d5fb497 100644
--- a/doc/xschem_man/symbol_property_syntax.html
+++ b/doc/xschem_man/symbol_property_syntax.html
@@ -575,8 +575,16 @@ verilog_format="xnor #(@risedel , @falldel ) @name ( @@Z , @@A , @@B );"
     These tokens may be placed as text in the symbol graphic window, not in format strings.
   </p>
   <li><kbd>@#pin_name:net_name</kbd></li>
+
   <li><kbd>@#n:net_name</kbd></li>
-  <p> these expand to the net name attached to pin with name <kbd>pin_name</kbd> or with sequence number <kbd>n</kbd>. </p>
+  <p> these expand to the net name attached to pin with name <kbd>pin_name</kbd> or with
+    sequence number <kbd>n</kbd>. </p>
+
+  <li><kbd>@#pin_name:resolved_net</kbd></li>
+  <li><kbd>@#n:resolved_net</kbd></li>
+  <p> these expand to the full hierarchy name of the net attached to pin with name <kbd>pin_name</kbd> or with 
+    sequence number <kbd>n</kbd>. </p>
+
   <li><kbd>@sch_last_modified</kbd></li>
   <p>
    this indicates the last modification time of the <kbd>.sch</kbd> file of the symbol.
diff --git a/doc/xschem_man/tutorial_create_symbol.html b/doc/xschem_man/tutorial_create_symbol.html
index d5ce767c..f9398623 100644
--- a/doc/xschem_man/tutorial_create_symbol.html
+++ b/doc/xschem_man/tutorial_create_symbol.html
@@ -73,7 +73,7 @@ extra="power ground"
 extra_pinnumber="14 7"
   </pre><br>
   <p class="important">Instead of the <kbd>q</kbd> key the attribute dialog box can also be displayed
-  by pressing the <kbd>right</kbd> mouse button</p><br>
+  by <kbd>double clicking</kbd> the left mouse button</p><br>
 
   these attributes specify the gate type, the format for tedax netlist, the <kbd>template</kbd> attribute
   specifies default values for attributes and defines pin connection for VDD and VSS that are
diff --git a/xschem_library/pcb/74ls00.sym b/xschem_library/pcb/74ls00.sym
index a80fc1b9..05bb4675 100644
--- a/xschem_library/pcb/74ls00.sym
+++ b/xschem_library/pcb/74ls00.sym
@@ -1,7 +1,8 @@
-v {xschem version=2.9.8 file_version=1.2}
+v {xschem version=3.4.4 file_version=1.2
+}
 G {}
 K {type=nand
-format="@name @pinlist @value"
+format="@name @pinlist @power @ground @symname"
 verilog_format="nand #(@risedel , @falldel ) @name ( @#2 , @#0 , @#1 );"
 risedel=100
 falldel=200 
diff --git a/xschem_library/pcb/7805.sym b/xschem_library/pcb/7805.sym
index 5ccd2db1..c0e613ff 100644
--- a/xschem_library/pcb/7805.sym
+++ b/xschem_library/pcb/7805.sym
@@ -1,7 +1,8 @@
-v {xschem version=2.9.8 file_version=1.2}
+v {xschem version=3.4.4 file_version=1.2
+}
 G {}
 K {type=regulator
-format="@spiceprefix@name @pinlist r@symname"
+format="@spiceprefix@name @pinlist @symname"
 verilog_format="assign @#2 = @#0 ;"
 
 tedax_format="footprint @name @footprint
diff --git a/xschem_library/pcb/pcb_test1.sch b/xschem_library/pcb/pcb_test1.sch
index 7b816ad1..5f5ec61c 100644
--- a/xschem_library/pcb/pcb_test1.sch
+++ b/xschem_library/pcb/pcb_test1.sch
@@ -1,4 +1,5 @@
-v {xschem version=3.0.0 file_version=1.2 }
+v {xschem version=3.4.4 file_version=1.2
+}
 G {}
 K {}
 V {}
@@ -29,16 +30,20 @@ N 520 -460 760 -460 {lab=A}
 N 580 -420 760 -420 {lab=B}
 N 580 -420 580 -350 {lab=B}
 N 520 -350 580 -350 {lab=B}
-N 480 -460 520 -460 {}
+N 480 -460 520 -460 {
+lab=A}
 C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
 C {74ls00.sym} 420 -350 0 0 {name=U1:2  risedel=100 falldel=200}
 C {74ls00.sym} 870 -440 0 0 {name=U1:1  risedel=100 falldel=200}
 C {lab_pin.sym} 970 -440 0 1 {name=p0 lab=OUTPUT_Y}
 C {74ls00.sym} 420 -460 0 0 {name=U1:4 risedel=100 falldel=200
-url="http://www.engrcs.com/components/74LS00.pdf" 
-power=VCC5 
+url="http://www.engrcs.com/components/74LS00.pdf"
 
-___net:14=VCC5
+#="you can reroute implicit power pins in the following two ways:"
+__power=VCC5 
+__net:14=VCC5
+
+#="You can reassign pin attrinutes this way:"
 ___pinnumber(B)=111:222:333:444}
 C {7805.sym} 730 -190 0 0 {name=U0 
 spiceprefix=X