From 52c65f9d3410038f457ef727b5a0c0cbf29f3b4b Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Wed, 1 Nov 2023 21:06:08 +0100 Subject: [PATCH] update delta_sigma example ( Use different RUP/RDOWN resistances for inv / buf ) --- xschem_library/ngspice/adc.sch | 4 ++-- xschem_library/ngspice/buf_ngspice.sch | 16 ++++++++-------- xschem_library/ngspice/buf_ngspice.sym | 9 +++++---- xschem_library/ngspice/delta_sigma.sch | 16 ++++++++-------- xschem_library/ngspice/flip_flop_ngspice.sch | 10 ++++++---- xschem_library/ngspice/inv_ngspice.sch | 12 ++++++------ xschem_library/ngspice/inv_ngspice.sym | 9 +++++---- xschem_library/ngspice/keeper_ngspice.sch | 6 +++--- 8 files changed, 43 insertions(+), 39 deletions(-) diff --git a/xschem_library/ngspice/adc.sch b/xschem_library/ngspice/adc.sch index 25c47d2d..285ce8b8 100644 --- a/xschem_library/ngspice/adc.sch +++ b/xschem_library/ngspice/adc.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -144,7 +144,7 @@ C {lab_pin.sym} 1520 -390 0 0 {name=p1 lab=RST} C {spice_probe.sym} 840 -250 0 0 {name=p6 attrs=""} C {spice_probe.sym} 710 -410 0 0 {name=p17 attrs=""} C {spice_probe.sym} 1540 -270 0 0 {name=p18 attrs=""} -C {inv_ngspice.sym} 1040 -410 0 0 {name=x11 ROUT=1000 net_name=true} +C {inv_ngspice.sym} 1040 -410 0 0 {name=x11 net_name=true RUP=1000} C {lab_wire.sym} 1130 -410 0 0 {name=l2 lab=QN} C {spice_probe.sym} 1090 -410 0 0 {name=p19 attrs=""} C {ipin.sym} 310 -370 0 0 {name=p242 lab=VREF} diff --git a/xschem_library/ngspice/buf_ngspice.sch b/xschem_library/ngspice/buf_ngspice.sch index 26f19145..e0c19aa4 100644 --- a/xschem_library/ngspice/buf_ngspice.sch +++ b/xschem_library/ngspice/buf_ngspice.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -24,8 +24,10 @@ K {} V {} S {} E {} -N 470 -470 470 -430 { lab=#net1} -N 470 -470 540 -470 { lab=#net1} +T {@name +@FUNC} 490 -520 0 0 0.2 0.2 {name=B2} +N 470 -470 470 -430 { lab=X1} +N 470 -470 540 -470 { lab=X1} N 470 -370 470 -320 { lab=0} N 600 -470 670 -470 { lab=Y1} N 320 -470 360 -470 { lab=A1} @@ -36,11 +38,6 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1+tanh((V(A1)-VCC/2)*1 } C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0} -C {res.sym} 570 -470 1 0 {name=R1 -value='ROUT' -footprint=1206 -device=resistor -m=1} C {lab_pin.sym} 670 -470 0 1 {name=l5 sig_type=std_logic lab=Y1} C {lab_pin.sym} 130 -240 0 1 {name=l6 sig_type=std_logic lab=A1} C {lab_pin.sym} 260 -240 0 0 {name=l7 sig_type=std_logic lab=Y1} @@ -48,3 +45,6 @@ C {parax_cap.sym} 620 -460 0 0 {name=C3 gnd=0 value=8f m=1} C {parax_cap.sym} 360 -460 0 0 {name=C1 gnd=0 value=4f m=1} C {vsource.sym} 290 -240 1 0 {name=V1 value=0} C {vsource.sym} 100 -240 1 0 {name=V2 value=0} +C {bsource.sym} 570 -470 3 1 {name=B2 VAR=I FUNC="'v(X1,Y1) > 0 ? v(X1,Y1) / RUP : v(X1,Y1) / RDOWN'" +hide_texts=1} +C {lab_pin.sym} 470 -470 0 0 {name=l4 sig_type=std_logic lab=X1} diff --git a/xschem_library/ngspice/buf_ngspice.sym b/xschem_library/ngspice/buf_ngspice.sym index b83a8f76..0a068d16 100644 --- a/xschem_library/ngspice/buf_ngspice.sym +++ b/xschem_library/ngspice/buf_ngspice.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -21,8 +21,8 @@ v {xschem version=3.4.4 file_version=1.2 } G {} K {type=subcircuit -format="@name @pinlist @symname ROUT=@ROUT" -template="name=x1 ROUT=1000" +format="@name @pinlist @symname RUP=@RUP RDOWN=@RDOWN" +template="name=x1 RUP=2000 RDOWN=1000" } V {} S {} @@ -38,6 +38,7 @@ T {@symname} -47.5 34 0 0 0.3 0.3 {} T {@name} 25 -22 0 0 0.2 0.2 {} T {Y} 7.5 -6.5 0 1 0.2 0.2 {} T {A} -17.5 -6.5 0 0 0.2 0.2 {} -T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {} +T {RUP=@RUP +RDOWN=@RDOWN} -25 -52 0 0 0.2 0.2 {} T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15} T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15} diff --git a/xschem_library/ngspice/delta_sigma.sch b/xschem_library/ngspice/delta_sigma.sch index ffd97dcf..4985b329 100644 --- a/xschem_library/ngspice/delta_sigma.sch +++ b/xschem_library/ngspice/delta_sigma.sch @@ -124,25 +124,25 @@ value="pwl + 6.001u 0.97 9u 0.97"} C {lab_pin.sym} 270 -510 0 0 {name=p1 lab=0} C {lab_pin.sym} 270 -570 0 0 {name=p2 lab=SIG_IN} -C {vsource.sym} 520 -550 0 0 {name=v1 +C {vsource.sym} 520 -540 0 0 {name=v1 value="pulse 0 VCC 100n 100p 100p 9.9n 20n" xvalue="sin 0.2 1.8 1u 0" } -C {lab_pin.sym} 520 -520 0 0 {name=p6 lab=0} -C {lab_pin.sym} 520 -580 0 0 {name=p7 lab=CK} +C {lab_pin.sym} 520 -510 0 0 {name=p6 lab=0} +C {lab_pin.sym} 520 -570 0 0 {name=p7 lab=CK} C {vsource.sym} 390 -640 0 0 {name=v5 value=VCC} C {lab_pin.sym} 390 -610 0 0 {name=p17 lab=0} C {lab_pin.sym} 390 -570 0 0 {name=p18 lab=VSS} C {vsource.sym} 390 -540 0 0 {name=v6 value=0} C {lab_pin.sym} 390 -510 0 0 {name=p19 lab=0} -C {lab_pin.sym} 520 -680 0 0 {name=p55 lab=RST} -C {vsource.sym} 520 -650 0 0 {name=v7 value="pwl 0 VCC +C {lab_pin.sym} 520 -670 0 0 {name=p55 lab=RST} +C {vsource.sym} 520 -640 0 0 {name=v7 value="pwl 0 VCC + 1u VCC 1.001u 0 3u 0 3.001u VCC + 4u VCC 4.001u 0 6u 0 6.001u VCC + 7u VCC 7.001u 0 9u 0 9.001u VCC" } -C {lab_pin.sym} 520 -620 0 0 {name=p56 lab=0} +C {lab_pin.sym} 520 -610 0 0 {name=p56 lab=0} C {vdd.sym} 390 -670 0 0 {name=l2 lab=VCC} C {adc.sym} 620 -190 0 0 {name=x1} C {lab_pin.sym} 700 -220 0 1 {name=p38 lab=CODE[5:0]} @@ -153,8 +153,8 @@ C {lab_pin.sym} 540 -160 0 0 {name=p42 lab=RST} C {spice_probe.sym} 270 -670 0 0 {name=p3 attrs=""} C {spice_probe.sym} 390 -670 0 0 {name=p4 attrs=""} C {spice_probe.sym} 270 -570 0 0 {name=p5 attrs=""} -C {spice_probe.sym} 520 -580 0 0 {name=p8 attrs=""} -C {spice_probe.sym} 520 -680 0 0 {name=p9 attrs=""} +C {spice_probe.sym} 520 -570 0 0 {name=p8 attrs=""} +C {spice_probe.sym} 520 -670 0 0 {name=p9 attrs=""} C {spice_probe.sym} 700 -220 0 0 {name=p10 attrs=""} C {launcher.sym} 1270 -90 0 0 {name=h5 descr="Select arrow and diff --git a/xschem_library/ngspice/flip_flop_ngspice.sch b/xschem_library/ngspice/flip_flop_ngspice.sch index 28940bcd..8286a2ae 100644 --- a/xschem_library/ngspice/flip_flop_ngspice.sch +++ b/xschem_library/ngspice/flip_flop_ngspice.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -56,14 +56,15 @@ C {lab_pin.sym} 740 -420 0 0 {name=l7 sig_type=std_logic lab=0} C {lab_pin.sym} 760 -420 0 1 {name=l8 sig_type=std_logic lab=CLK} C {keeper_ngspice.sym} 1030 -570 0 0 {name=x3} C {lab_pin.sym} 500 -480 0 1 {name=l9 sig_type=std_logic lab=DI} -C {buf_ngspice.sym} 1070 -460 0 0 {name=x4 ROUT=100} +C {buf_ngspice.sym} 1070 -460 0 0 {name=x4 RUP=100 RDOWN=100} C {lab_pin.sym} 970 -480 0 0 {name=l10 sig_type=std_logic lab=QI} C {lab_pin.sym} 1160 -460 0 1 {name=l11 sig_type=std_logic lab=Q} C {switch_ngspice.sym} 990 -330 0 0 {name=S3 model=SWITCH} C {lab_pin.sym} 990 -260 0 0 {name=l2 sig_type=std_logic lab=0} C {lab_pin.sym} 950 -310 0 0 {name=l3 sig_type=std_logic lab=0} C {lab_pin.sym} 950 -330 0 0 {name=l12 sig_type=std_logic lab=RST} -C {buf_ngspice.sym} 630 -460 0 0 {name=x1} +C {buf_ngspice.sym} 630 -460 0 0 {name=x1 +RUP=1000} C {switch_ngspice.sym} 430 -460 1 1 {name=S4 model=SWITCH} C {lab_pin.sym} 430 -420 0 1 {name=l13 sig_type=std_logic lab=VCC} C {lab_pin.sym} 410 -420 0 0 {name=l14 sig_type=std_logic lab=RST} @@ -71,4 +72,5 @@ C {switch_ngspice.sym} 520 -330 0 0 {name=S5 model=SWITCH} C {lab_pin.sym} 520 -260 0 0 {name=l15 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -310 0 0 {name=l16 sig_type=std_logic lab=0} C {lab_pin.sym} 480 -330 0 0 {name=l17 sig_type=std_logic lab=RST} -C {buf_ngspice.sym} 170 -460 0 0 {name=x5} +C {buf_ngspice.sym} 170 -460 0 0 {name=x5 +RUP=1000} diff --git a/xschem_library/ngspice/inv_ngspice.sch b/xschem_library/ngspice/inv_ngspice.sch index c6d84b0c..fa6b4f7f 100644 --- a/xschem_library/ngspice/inv_ngspice.sch +++ b/xschem_library/ngspice/inv_ngspice.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -24,6 +24,8 @@ K {} V {} S {} E {} +T {@name +@FUNC} 490 -520 0 0 0.2 0.2 {name=B2} N 470 -470 470 -430 { lab=#net1} N 470 -470 540 -470 { lab=#net1} N 470 -370 470 -320 { lab=0} @@ -36,11 +38,6 @@ C {bsource.sym} 470 -400 0 1 {name=B1 VAR=V FUNC="'VCC/2*(1-tanh((V(A1)-VCC/2)*1 } C {lab_pin.sym} 320 -470 0 0 {name=l2 sig_type=std_logic lab=A1} C {lab_pin.sym} 470 -320 0 0 {name=l3 sig_type=std_logic lab=0} -C {res.sym} 570 -470 1 0 {name=R1 -value='ROUT' -footprint=1206 -device=resistor -m=1} C {lab_pin.sym} 670 -470 0 1 {name=l5 sig_type=std_logic lab=Y1} C {lab_pin.sym} 130 -240 0 1 {name=l6 sig_type=std_logic lab=A1} C {lab_pin.sym} 260 -240 0 0 {name=l7 sig_type=std_logic lab=Y1} @@ -50,3 +47,6 @@ C {vsource.sym} 290 -240 1 0 {name=V1 value=0 savecurrent=1} C {vsource.sym} 100 -240 1 0 {name=V2 value=0 savecurrent=1} +C {bsource.sym} 570 -470 3 1 {name=B2 VAR=I FUNC="'v(X1,Y1) > 0 ? v(X1,Y1) / RUP : v(X1,Y1) / RDOWN'" +hide_texts=1} +C {lab_pin.sym} 470 -470 0 0 {name=l4 sig_type=std_logic lab=X1} diff --git a/xschem_library/ngspice/inv_ngspice.sym b/xschem_library/ngspice/inv_ngspice.sym index 2e7c71b7..28a81038 100644 --- a/xschem_library/ngspice/inv_ngspice.sym +++ b/xschem_library/ngspice/inv_ngspice.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -25,8 +25,8 @@ verilog_primitive=true vhdl_primitive=true vhdl_format="@@Y <= @@A after 90 ps;" verilog_format="assign #90 @@Y = ~@@A ;" -format="@name @pinlist @symname ROUT=@ROUT" -template="name=x1 ROUT=1000" +format="@name @pinlist @symname RUP=@RUP RDOWN=@RDOWN" +template="name=x1 RUP=2000 RDOWN=1000" } V {} S {} @@ -43,6 +43,7 @@ T {@symname} -47.5 24 0 0 0.3 0.3 {} T {@name} 25 -22 0 0 0.2 0.2 {} T {Y} 7.5 -6.5 0 1 0.2 0.2 {} T {A} -17.5 -6.5 0 0 0.2 0.2 {} -T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {} T {@#1:net_name} -22.5 6.25 0 1 0.15 0.15 {layer=15} T {@#0:net_name} 17.5 6.25 0 0 0.15 0.15 {layer=15} +T {RUP=@RUP +RDOWN=@RDOWN} -25 -52 0 0 0.2 0.2 {} diff --git a/xschem_library/ngspice/keeper_ngspice.sch b/xschem_library/ngspice/keeper_ngspice.sch index e593892b..ae250cb3 100644 --- a/xschem_library/ngspice/keeper_ngspice.sch +++ b/xschem_library/ngspice/keeper_ngspice.sch @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.5 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -33,6 +33,6 @@ N 370 -200 400 -200 { lab=Y} N 220 -250 260 -250 { lab=A} C {ipin.sym} 220 -250 0 0 {name=p1 lab=A} C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"} -C {inv_ngspice.sym} 330 -200 0 0 {name=x1 ROUT=1000} -C {inv_ngspice.sym} 330 -300 0 1 {name=x2 ROUT=300k} +C {inv_ngspice.sym} 330 -200 0 0 {name=x1} +C {inv_ngspice.sym} 330 -300 0 1 {name=x2 RUP=300k RDOWN=200k} C {lab_pin.sym} 400 -250 0 1 {name=l2 sig_type=std_logic lab=Y}