diff --git a/doc/xschem_man/tutorial_xschem_slides01.html b/doc/xschem_man/tutorial_xschem_slides01.html
index 8e0349aa..f1d0bade 100644
--- a/doc/xschem_man/tutorial_xschem_slides01.html
+++ b/doc/xschem_man/tutorial_xschem_slides01.html
@@ -20,7 +20,7 @@ p{padding: 15px  30px 10px;}
 
 
  <!-- slide title -->
- <h1>PRESENTATION OUTLINE</h1>
+ <h1>XSCHEM SCHEMATIC EDITOR PRESENTATION OUTLINE</h1>
 
  <h1 style="text-align:left; margin-left:0;">
   <ul style="margin-left:0;max-width:50%;">
diff --git a/doc/xschem_man/tutorial_xschem_slides02.html b/doc/xschem_man/tutorial_xschem_slides02.html
index c3734ee1..2547f88b 100644
--- a/doc/xschem_man/tutorial_xschem_slides02.html
+++ b/doc/xschem_man/tutorial_xschem_slides02.html
@@ -22,19 +22,16 @@ p{padding: 15px  30px 10px;}
  <!-- slide title -->
  <h1>WHY XSCHEM?</h1>
   <h2 style="text-align:left; margin-left:3%;">
-   Ex frustrated Cadence Virtuoso user.<br>
+   Have been a Cadence Virtuoso user for many years, in different companies.<br>
   </h2>
   <h3 style="text-align:left; margin-left:3%;margin-top:10px;">
    <ul>
-    <li>Don't want to wait a minute for a simple amplifier netlist.</li>
-    <li>Creating new components was way too complicated (you need a CDF, ask your CAD support and file a ticket).</li>
+    <li>Long startup time</li>
+    <li>Creating new components way too complicated (you need a CDF, ask your CAD support and file a ticket).</li>
     <li>Memory Hog, keeps growing until all Virtual memory exhausted, then crash.</li>
-    <li>Start your icfb session, go get a coffee, when back it's hopefully up and running.</li>
     <li>One process handles all design windows. Process crashes, all work on all windows lost.</li>
-    <li>Many functions (search/replace/highlight and others) take way too long
-        to complete. Everything is done in skill.</li>
+    <li>Netlist extraction and many other functions are slow since all is implemented in skill language.</li>
     <li>Proprietary file format.</li>
-    <li>Computation intensive tasks should not be done in any scripting language (Tcl, Skill, Lisp, Python)</li>
    </ul>
   </h3>
 
diff --git a/doc/xschem_man/tutorial_xschem_slides03.html b/doc/xschem_man/tutorial_xschem_slides03.html
index 67ad06e0..044c7999 100644
--- a/doc/xschem_man/tutorial_xschem_slides03.html
+++ b/doc/xschem_man/tutorial_xschem_slides03.html
@@ -26,10 +26,9 @@ p{padding: 15px  30px 10px;}
   <h3 style="text-align:left; margin-left:3%;">
    <ul>
     <li>Started in 1998 as a hobby home project when i was working at STM.</li>
-    <li>First versions were developed on solaris sparc, then on linux.</li>
+    <li>First versions were developed on Solaris Sparc, then on linux.</li>
     <li>Subversion local repository in 2007.</li>
     <li><a href="https://sourceforge.net/projects/xschem">Sourceforge</a> svn repository in December 2016.</li>
-    <li>Cairo Text option for fonts added in 2017.</li>
     <li>Development boost happened in 2018 to present:</li>
      <ol>
        <li>More graphic primitives (polygons, arcs, circles).</li>
diff --git a/doc/xschem_man/tutorial_xschem_slides04.html b/doc/xschem_man/tutorial_xschem_slides04.html
index 76852a12..a277b852 100644
--- a/doc/xschem_man/tutorial_xschem_slides04.html
+++ b/doc/xschem_man/tutorial_xschem_slides04.html
@@ -30,12 +30,12 @@ p{padding: 15px  30px 10px;}
    <li>A hierarchical design tool: wrap (parametric) sub-blocks into symbols and use them multiple times.</li>
    <li>Has syntax for vector nets (bus notation) like DATA[7:0], WORD[7:0,15:8] as well as vector
        instance placements like Xinv[7:0], to handle repetitive components.</li>
-   <li>Fast: Performance is important. Editing a schematic with 100K instances MUST not be a problem.</li>
+   <li>Fast: Performance is important. Editing a schematic with 100K instances MUST not be a problem.
+       Netlist extraction must be instant (&lt;500ms) on small to medium designs.</li>
    <li>Xschem knows the connectivity. Netlist build is embedded in the core.</li>
    <li>Verilog, VHDL, Spice, tEDAx netlist backends. Adding another backend is not difficult.</li>
    <li>Intensive and time consuming computations all done in pure C.</li>
    <li>Tcl-tk used for GUI and scripting language. Direct Xlib drawing.</li>
-   <li>Netlist extraction must be instant (&lt;500ms) on small to medium designs.</li>
   </ul>
  </h3>
  </div>
@@ -50,7 +50,7 @@ p{padding: 15px  30px 10px;}
    <li>A Gtk or Qt project. Xschem will not bitrot over time due to changed library APIs.
    <li>A layout tool, although the graphical engine was designed to support layout as well.</li>
    <li>A circuit simulator.</li>
-   <li>Super easy to use: there is a learning curve.</li>
+   <li>Easy to use: there is a learning curve.</li>
    <li>A memory hog: XSCHEM with a medium design loaded requires 54M virtual memory, 24M resident set. 
        A full chip design can be handled with a 1GB RAM system and low end processor.
    <li>A C++, C99, C11 project: all code is ANSI-C C89, works on old Solaris, Irix machines, compiles on 32bit, 64 bit and on armhf.
diff --git a/doc/xschem_man/tutorial_xschem_slides05.html b/doc/xschem_man/tutorial_xschem_slides05.html
index 9550fdef..eb0f3bbc 100644
--- a/doc/xschem_man/tutorial_xschem_slides05.html
+++ b/doc/xschem_man/tutorial_xschem_slides05.html
@@ -48,9 +48,7 @@ p{padding: 15px  30px 10px;}
      <tr><td>Bus notation for nets and components.</td><td>Yes.</td></tr>
      <tr><td>Portability.</td><td>All UNIX systems with Tcl and X11, Windows with VS and Active-Tcl.</td></tr>
      <tr><td>Netlisting performance.</td><td>Extremely fast, Complex system with 59 sub blocks netlisted in VHDL in &lt; 1 second on a Linux laptop.</td></tr>
-     <tr><td>Startup time.</td><td>Fast (&lt;1 sec).</td></tr>
      <tr><td>Primitive component creation with arbitrary code for VHDL/SPICE/verilog.</td><td>Works out of the box with very simple property strings.</td></tr>
-     <tr><td>Parametrized sub blocks.</td><td>Yes.</td></tr>
      <tr><td>Single / split file netlisting.</td><td>Yes, any supported netlist formats.</td></tr>
      <tr><td>Mixed mode netlisting, symbol based.</td><td>Yes, in split netlisting mode.</td></tr>
      <tr><td>Automatic symbol creation from schematic and vice-versa.</td><td>Yes.</td></tr>