diff --git a/xschem_library/examples/0_examples_top.sch b/xschem_library/examples/0_examples_top.sch
index c911a674..40b18ac3 100644
--- a/xschem_library/examples/0_examples_top.sch
+++ b/xschem_library/examples/0_examples_top.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.5 file_version=1.2
+v {xschem version=3.4.6RC file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -99,6 +99,7 @@ T {Simulation
 Graphs
 } 1530 -550 0 0 0.6 0.6 {layer=4}
 T {Bus rippers} 580 -380 0 0 0.6 0.6 {layer=4}
+T {Verilog-A example} 800 -940 0 0 0.4 0.4 {}
 N 910 -410 940 -410 {lab=#net1}
 N 860 -380 860 -360 {lab=#net2}
 N 860 -380 920 -380 {lab=#net2}
@@ -1499,3 +1500,4 @@ C {autozero_comp.sym} 480 -500 0 0 {name=x29}
 C {tb_symbol_include.sym} 480 -780 0 0 {name=x30}
 C {intuitive_interface_cheatsheet.sym} 1060 -100 0 0 {name=x31}
 C {test_nyquist.sym} 480 -460 0 0 {name=x32}
+C {tb_diff_amp.sym} 890 -890 0 0 {name=x33}
diff --git a/xschem_library/ngspice/diff_amp.sym b/xschem_library/ngspice/diff_amp.sym
new file mode 100644
index 00000000..44a0d646
--- /dev/null
+++ b/xschem_library/ngspice/diff_amp.sym
@@ -0,0 +1,38 @@
+v {xschem version=3.4.6RC file_version=1.2
+}
+G {}
+K {type=opamp_va
+format="@spiceprefix@name @@OUT @@IN1 @@IN2 @model"
+
+template="name=U1 model=diff_amp_cell spiceprefix=X"
+
+device_model="tcleval(
+.subckt diff_amp_cell OUT IN1 IN2
+N1 out in1 in2 diff_amp_model
+.ends diff_amp_cell
+
+.model diff_amp_model diff_amp
+
+.control
+* following line specifies the location for the .osdi file so ngspice can use it.
+pre_osdi $USER_CONF_DIR/xschem_library/diff_amp.osdi
+.endc
+)"
+}
+V {}
+S {}
+E {}
+L 4 -100 -40 -80 -40 {}
+L 4 80 0 100 0 {}
+L 4 -100 40 -80 40 {}
+B 5 97.5 -2.5 102.5 2.5 {name=OUT dir=out}
+B 5 -102.5 -42.5 -97.5 -37.5 {name=IN1 dir=in}
+B 5 -102.5 37.5 -97.5 42.5 {name=IN2 dir=in}
+P 4 4 -80 80 -80 -80 80 -0 -80 80 {}
+T {@symname} -64 -6 0 0 0.3 0.3 {}
+T {@name} 85 -22 0 0 0.2 0.2 {}
+T {IN1} -75 -44 0 0 0.2 0.2 {}
+T {OUT} 65 -4 0 1 0.2 0.2 {}
+T {IN2} -75 36 0 0 0.2 0.2 {}
+T {Ensure port order matches the
+order in the verilog-A file.} -30 -70 0 0 0.1 0.1 {hide=instance}
diff --git a/xschem_library/ngspice/tb_diff_amp.sch b/xschem_library/ngspice/tb_diff_amp.sch
new file mode 100644
index 00000000..86c92a6f
--- /dev/null
+++ b/xschem_library/ngspice/tb_diff_amp.sch
@@ -0,0 +1,110 @@
+v {xschem version=3.4.6RC file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+B 2 840 -900 1640 -500 {flags=graph
+y1=0
+y2=6
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=6
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node="b
+a"
+color="6 4"
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+B 2 840 -500 1640 -100 {flags=graph
+y1=-30
+y2=30
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=6
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node=z
+color=7
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
+P 4 5 140 -620 140 -870 710 -870 710 -620 140 -620 {}
+P 4 7 410 -620 410 -560 420 -560 410 -540 400 -560 410 -560 410 -620 {}
+T {// importing libs
+
+`include "discipline.h"
+
+module diff_amp(
+  output electrical out,
+  input electrical in1,
+  input electrical in2);
+
+parameter real gain = 10; // setting gain to 10 of the differential amplifier
+
+analog begin
+
+    V(out) <+ gain * (V(in1, in2));
+    // V(out) <+ 2 * atan( gain / 2 * V(in1, in2) );
+
+end
+endmodule} 150 -860 0 0 0.2 0.2 {font=monospace}
+T {create a diff_amp.va file with following code 
+and compile it into a .osdi file with openvaf.} 190 -930 0 0 0.4 0.4 {}
+N 180 -450 320 -450 {lab=B}
+N 80 -530 320 -530 {lab=A}
+N 520 -490 640 -490 {lab=Z}
+N 60 -290 180 -290 {lab=0}
+N 180 -330 180 -290 {lab=0}
+N 80 -330 80 -290 {lab=0}
+N 80 -530 80 -390 {lab=A}
+N 180 -450 180 -390 {lab=B}
+C {diff_amp.sym} 420 -490 0 0 {name=U1}
+C {lab_pin.sym} 640 -490 0 1 {name=p1 sig_type=std_logic lab=Z}
+C {lab_pin.sym} 80 -530 0 0 {name=p2 sig_type=std_logic lab=A}
+C {lab_pin.sym} 180 -450 0 0 {name=p3 sig_type=std_logic lab=B}
+C {vsource.sym} 80 -360 0 0 {name=V1 value=3.1 savecurrent=false}
+C {vsource.sym} 180 -360 0 0 {name=V2 value=3 savecurrent=false}
+C {lab_pin.sym} 60 -290 0 0 {name=p4 sig_type=std_logic lab=0}
+C {code_shown.sym} 240 -320 0 0 {name=COMMANDS only_toplevel=false value="
+.options savecurrents
+.control
+  save all
+  op
+  remzerovec
+  write tb_diff_amp.raw
+  dc V1 0 6 0.01
+  set appendwrite
+  remzerovec
+  write tb_diff_amp.raw
+  quit 0
+.endc
+"}
+C {launcher.sym} 670 -120 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/tb_diff_amp.raw dc"
+}
+C {title.sym} 160 -30 0 0 {name=l1 author="Phillip Baade-Pedersen"}
+C {launcher.sym} 670 -170 0 0 {name=h1
+descr="OP annotate" 
+tclcommand="xschem annotate_op"
+}
diff --git a/xschem_library/ngspice/tb_diff_amp.sym b/xschem_library/ngspice/tb_diff_amp.sym
new file mode 100644
index 00000000..3ca9999d
--- /dev/null
+++ b/xschem_library/ngspice/tb_diff_amp.sym
@@ -0,0 +1,11 @@
+v {xschem version=3.4.6RC file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -67.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}