From 48b1f8eb31605edfa5991e105257548e5ca51c12 Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Mon, 1 Apr 2024 04:06:11 +0200
Subject: [PATCH] update LCC_instances.sch (3)

---
 tests/xschemtest.tcl                      |   2 +-
 xschem_library/examples/LCC_instances.sch | 198 +++++++++++++++-------
 xschem_library/examples/bus_keeper.sch    |  28 +--
 xschem_library/examples/cmos_inv.sch      |  26 ++-
 4 files changed, 169 insertions(+), 85 deletions(-)

diff --git a/tests/xschemtest.tcl b/tests/xschemtest.tcl
index e5477907..db76ec0e 100644
--- a/tests/xschemtest.tcl
+++ b/tests/xschemtest.tcl
@@ -199,7 +199,7 @@ proc netlist_test {} {
     loading.sch             vhdl       2975204502
     mos_power_ampli.sch     spice      3405708328
     hierarchical_tedax.sch  tedax       998070173
-    LCC_instances.sch       spice      1888015492
+    LCC_instances.sch       spice       372367338
     pcb_test1.sch           tedax      1925087189
     test_doublepin.sch      spice      4159808692
     simulate_ff.sch         spice       574849766
diff --git a/xschem_library/examples/LCC_instances.sch b/xschem_library/examples/LCC_instances.sch
index a2a5142b..9183902d 100644
--- a/xschem_library/examples/LCC_instances.sch
+++ b/xschem_library/examples/LCC_instances.sch
@@ -27,13 +27,13 @@ V {}
 S {
 }
 E {}
-L 4 210 -300 230 -320 {}
-L 4 210 -300 250 -300 {}
-L 4 230 -320 250 -300 {}
-L 4 230 -220 250 -240 {}
-L 4 210 -240 250 -240 {}
-L 4 210 -240 230 -220 {}
-L 4 230 -300 230 -240 {}
+L 4 220 -310 240 -330 {}
+L 4 220 -310 260 -310 {}
+L 4 240 -330 260 -310 {}
+L 4 240 -230 260 -250 {}
+L 4 220 -250 260 -250 {}
+L 4 220 -250 240 -230 {}
+L 4 240 -310 240 -250 {}
 L 4 350 -580 370 -560 {dash=3}
 L 4 370 -600 370 -560 {dash=3}
 L 4 350 -580 370 -600 {dash=3}
@@ -42,41 +42,86 @@ L 4 1420 -730 1440 -750 {dash=3}
 L 4 1420 -770 1420 -730 {dash=3}
 L 4 1420 -770 1440 -750 {dash=3}
 L 4 1350 -750 1420 -750 {dash=3}
-B 2 790 -490 1410 -260 {flags=graph,unlocked 
-y1 = 0
-y2 = 3
-divy = 6
-x1=0
-x2=3
-divx=6
-node="a
-zz%0
-zz%1
-zzz
-xkeeper.y
-xkeeper.y%1"
-color="8 6 12 7 9 10"
-sweep="v(a)"
-dataset=0
-hilight_wave=2}
 B 2 10 -1080 340 -730 {flags=graph,unlocked 
 y1 = 0
 y2 = 3
 divy = 6
-x1=0
+x1=2.7755576e-17
 x2=3
 divx=6
 node="a z"
 color="7 6"
 sweep="z a"
-}
+rawfile=$netlist_dir/LCC_instances.raw
+sim_type=dc
+dataset=0}
+B 2 850 -270 1150 -60 {flags=graph
+y1=0
+y2=3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=3
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+
+
+dataset=0
+unitx=1
+logx=0
+logy=0
+
+rainbow=0
+sweep=a
+color="7 8 6"
+node="zz%0
+zz%1
+a%0"
+rawfile=$netlist_dir/LCC_instances.raw
+sim_type=tran
+hilight_wave=-1}
+B 2 850 -480 1150 -270 {flags=graph
+y1=0
+y2=3
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=3
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+
+
+dataset=0
+unitx=1
+logx=0
+logy=0
+
+rainbow=0
+sweep=a
+color="7 8 6"
+node="zz%0
+zz%1
+a%0"
+rawfile=$netlist_dir/LCC_instances.raw
+sim_type=dc
+hilight_wave=-1}
 B 8 255 -871.25 295 -831.25 {}
 B 8 113.75 -1002.5 153.75 -962.5 {}
 P 4 5 560 -700 560 -510 1350 -510 1350 -700 560 -700 {dash=3}
 P 4 5 820 -920 820 -730 1350 -730 1350 -920 820 -920 {dash=3}
-P 4 5 0 -1160 1840 -1160 1840 0 -0 0 0 -1160 {dash=4}
+P 4 5 0 -1160 1960 -1160 1960 0 -0 0 0 -1160 {dash=4}
 T {These 2 instances
-are equivalent} 260 -310 0 0 0.4 0.4 {}
+are equivalent} 270 -320 0 0 0.4 0.4 {}
 T {Example of using a schematic as a component instance
 instead of the usual symbol. LCC: Local Custom Cell.
 
@@ -90,19 +135,18 @@ and use arrow keys to zoom / pan waveforms} 10 -1150 0 0 0.3 0.3 {}
 T {Butterfly diagram
 of a sram cell} 460 -980 0 0 0.4 0.4 {layer=8}
 T {@symname
-@name} 1840 -1250 0 1 0.7 0.7 {}
-N 410 -100 410 -80 {lab=HALF}
-N 410 -190 430 -190 {lab=ZZZ}
-N 410 -190 410 -160 {lab=ZZZ}
-N 420 -400 420 -380 {lab=HALF}
-N 420 -490 740 -490 {lab=ZZ}
-N 420 -490 420 -460 {lab=ZZ}
-N 740 -240 1450 -240 {lab=#net1}
-N 320 -190 410 -190 {lab=ZZZ}
-N 330 -490 420 -490 {lab=ZZ}
-N 740 -320 740 -240 {
+@name} 1960 -1250 0 1 0.7 0.7 {}
+T {DC} 1160 -300 0 0 0.4 0.4 {}
+T {TRAN} 1160 -90 0 0 0.4 0.4 {}
+N 340 -90 340 -70 {lab=HALF}
+N 380 -190 400 -190 {lab=ZZZ}
+N 1240 -380 1240 -360 {lab=HALF}
+N 420 -490 1350 -490 {lab=ZZ}
+N 1350 -240 1450 -240 {lab=#net1}
+N 290 -190 380 -190 {lab=ZZZ}
+N 1350 -320 1350 -240 {
 lab=#net1}
-N 740 -490 740 -380 {
+N 1350 -490 1350 -380 {
 lab=ZZ}
 N 50 -280 50 -270 {
 lab=VDD}
@@ -113,34 +157,49 @@ lab=HALF}
 N 660 -860 680 -860 {lab=VDD}
 N 550 -860 600 -860 {
 lab=Z}
-N 570 -890 570 -860 {
+N 570 -910 570 -860 {
 lab=Z}
 N 630 -820 680 -820 {
 lab=VDD}
 N 680 -860 680 -820 {
 lab=VDD}
-C {vsource.sym} 50 -110 0 0 {name=V1 value="dc 0 pwl 0 0 1u 0 5u 3"
-savecurrent=1}
+N 60 -490 110 -490 {
+lab=A}
+N 150 -190 210 -190 {
+lab=A}
+N 1240 -460 1240 -440 {
+lab=#net2}
+N 340 -170 340 -150 {
+lab=#net3}
+N 410 -860 470 -860 {
+lab=A}
+C {vsource.sym} 50 -110 0 0 {name=V1 value="pwl 0 0 10u 3"
+savecurrent=1
+}
 C {lab_pin.sym} 50 -180 0 0 {name=p4 lab=A}
 C {lab_pin.sym} 50 -80 0 0 {name=p5 lab=0}
-C {code_shown.sym} 470 -340 0 0 {name=STIMULI
+C {code_shown.sym} 510 -450 0 0 {name=STIMULI
 only_toplevel=true
 tclcommand="xschem edit_vi_prop"
-value="* .ic v(L) = 3 v(R)=0
+value="* .options SRCSTEPS=0
 .control
 save all
 dc v1 0 3 0.001
-* tran 10n 10u uic
 write LCC_instances.raw
 set appendwrite 
 dc v1 3 0 -0.001
 write LCC_instances.raw
 op
 write LCC_instances.raw
+tran 10n 10u uic
+write LCC_instances.raw
+alter V1 pwl = [ 0 3 10u 0 ]
+tran 10n 10u uic
+write LCC_instances.raw
 * quit 0
 .endc
 "}
-C {code.sym} 840 -190 0 0 {name=MODEL
+C {code.sym} 1260 -170 0 0 {name=MODEL
 only_toplevel="true"
 tclcommand="xschem edit_vi_prop"
 value="************************************************
@@ -194,45 +253,56 @@ value="************************************************
 +WD    = 0.0 )
 
 "}
-C {lab_pin.sym} 240 -190 0 0 {name=p6 lab=A}
-C {lab_pin.sym} 430 -190 0 1 {name=p7 lab=ZZZ}
+C {lab_pin.sym} 150 -190 0 0 {name=p6 lab=A}
+C {lab_pin.sym} 400 -190 0 1 {name=p7 lab=ZZZ}
 C {vsource.sym} 50 -240 0 0 {name=V2 value=3
 savecurrent=1}
 C {lab_pin.sym} 50 -210 0 0 {name=p9 lab=0}
-C {res.sym} 410 -130 0 0 {name=R1
+C {res.sym} 340 -120 0 0 {name=R1
 value=80k
 footprint=1206
 device=resistor
 m=1}
-C {lab_pin.sym} 410 -80 0 0 {name=p10 lab=HALF}
+C {lab_pin.sym} 340 -70 0 0 {name=p10 lab=HALF}
 C {vsource.sym} 50 -370 0 0 {name=V3 value=1.5
 savecurrent=1}
 C {lab_pin.sym} 50 -420 0 0 {name=p11 lab=HALF}
 C {lab_pin.sym} 50 -340 0 0 {name=p12 lab=0}
-C {lab_pin.sym} 120 -490 0 0 {name=p13 lab=A}
-C {res.sym} 420 -430 0 0 {name=R2
+C {lab_pin.sym} 60 -490 0 0 {name=p13 lab=A}
+C {res.sym} 1240 -410 0 0 {name=R2
 value=80k
 footprint=1206
 device=resistor
 m=1}
-C {lab_pin.sym} 420 -380 0 0 {name=p15 lab=HALF}
+C {lab_pin.sym} 1240 -360 0 0 {name=p15 lab=HALF}
 C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
-C {cmos_inv.sch} 60 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
-C {cmos_inv.sym} 280 -190 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u}
-C {bus_keeper.sch} 1200 60 0 0 {name=Xkeeper WN_FB=6u WP_FB=12u}
-C {lab_pin.sym} 740 -490 0 1 {name=p1 lab=ZZ}
-C {lab_pin.sym} 470 -860 0 0 {name=p14 lab=A}
-C {lab_pin.sym} 570 -890 0 1 {name=p2 lab=Z}
+C {cmos_inv.sch} 50 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
+C {cmos_inv.sym} 250 -190 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u}
+C {bus_keeper.sch} 1290 60 0 0 {name=Xkeeper WN_FB=6u WP_FB=12u}
+C {lab_pin.sym} 1350 -490 0 1 {name=p1 lab=ZZ}
+C {lab_pin.sym} 410 -860 0 0 {name=p14 lab=A}
+C {lab_pin.sym} 570 -910 0 1 {name=p2 lab=Z}
 C {cmos_inv.sym} 510 -860 0 0 {name=Xinv1 WN=1u WP=1u LLN=2u LLP=2u}
 C {launcher.sym} 655 -1115 0 0 {name=h1 
-descr="Select arrow and 
-Ctrl-Left-Click to load/unload waveforms" 
+descr="load DC sim"
 tclcommand="
-xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
+xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw dc
 "
 }
-C {ammeter.sym} 740 -350 0 1 {name=Vmeas}
+C {ammeter.sym} 1350 -350 0 1 {name=Vmeas}
 C {vdd.sym} 50 -280 0 0 {name=l2 lab=VDD}
 C {nmos4.sym} 630 -840 3 0 {name=M1 model=n w=1u l=2u m=1 net_name=true}
 C {lab_pin.sym} 630 -860 3 1 {name=l4 sig_type=std_logic lab=0}
 C {vdd.sym} 680 -860 0 0 {name=l3 lab=VDD}
+C {launcher.sym} 655 -1045 0 0 {name=h2 
+descr="Annotate OP" 
+tclcommand="
+xschem annotate_op
+"
+}
+C {launcher.sym} 885 -1115 0 0 {name=h3 
+descr="load tran sim"
+tclcommand="
+xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw tran
+"
+}
diff --git a/xschem_library/examples/bus_keeper.sch b/xschem_library/examples/bus_keeper.sch
index 6156ceac..99fd46ac 100644
--- a/xschem_library/examples/bus_keeper.sch
+++ b/xschem_library/examples/bus_keeper.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -26,19 +26,25 @@ template="name=X1 WN_FB=1u WP_FB=2u"}
 V {}
 S {}
 E {}
-P 2 5 250 -930 250 -120 610 -120 610 -930 250 -930 {dash=5}
+P 2 5 160 -930 160 -120 610 -120 610 -930 160 -930 {dash=5}
 T {@name} 250 -965 0 0 0.5 0.5 {}
 T {@symname} 253.75 -115 0 0 0.5 0.5 {}
-N 250 -300 300 -300 {lab=A}
-N 280 -690 300 -690 {lab=A}
-N 280 -690 280 -300 {lab=A}
-N 510 -300 550 -300 {lab=Y}
+N 190 -690 190 -300 {lab=A}
 N 550 -690 550 -300 {lab=Y}
-N 510 -690 550 -690 {lab=Y}
-N 550 -240 550 -200 { lab=GND}
-C {cmos_inv.sch} 240 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u}
-C {cmos_inv.sch} 570 -460 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
-C {iopin.sym} 250 -300 0 1 {name=p1 lab=A}
+N 550 -240 550 -200 { lab=0}
+N 190 -300 210 -300 {
+lab=A}
+N 520 -300 550 -300 {
+lab=Y}
+N 520 -690 550 -690 {
+lab=Y}
+N 190 -690 210 -690 {
+lab=A}
+N 160 -300 190 -300 {
+lab=A}
+C {cmos_inv.sch} 150 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u}
+C {cmos_inv.sch} 580 -460 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
+C {iopin.sym} 160 -300 0 1 {name=p1 lab=A}
 C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
 C {capa.sym} 550 -270 0 0 {name=C1
 m=1
diff --git a/xschem_library/examples/cmos_inv.sch b/xschem_library/examples/cmos_inv.sch
index 3fe3d575..2cba45d7 100644
--- a/xschem_library/examples/cmos_inv.sch
+++ b/xschem_library/examples/cmos_inv.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -29,15 +29,13 @@ V {}
 S {}
 E {}
 A 15 90 -410 14.14213562373095 135 360 {dash=2}
-P 2 5 60 -450 270 -450 270 -90 60 -90 60 -450 {dash=5}
+P 2 5 60 -450 370 -450 370 -90 60 -90 60 -450 {dash=5}
 T {@name} 60 -465 0 0 0.2 0.2 {}
 T {@symname} 63.75 -85 0 0 0.2 0.2 {}
-N 80 -350 80 -170 {lab=A}
+N 80 -230 80 -170 {lab=A}
 N 60 -230 80 -230 {lab=A}
 N 140 -400 140 -380 {lab=VDD}
 N 140 -140 140 -120 {lab=0}
-N 240 -230 270 -230 {
-lab=Z}
 N 140 -230 180 -230 {
 lab=D}
 N 140 -320 140 -290 {
@@ -48,20 +46,30 @@ N 80 -350 100 -350 {
 lab=A}
 N 80 -170 100 -170 {
 lab=A}
-C {opin.sym} 270 -230 0 0 {name=p2 lab=Z}
+N 330 -230 370 -230 {
+lab=Z}
+N 240 -230 270 -230 {
+lab=#net2}
+N 140 -350 200 -350 {
+lab=VDD}
+N 140 -170 200 -170 {
+lab=0}
+N 80 -350 80 -230 {lab=A}
+C {opin.sym} 370 -230 0 0 {name=p2 lab=Z}
 C {ipin.sym} 60 -230 0 0 {name=p1 lab=A  goto=0}
 C {vdd.sym} 140 -400 0 0 {name=l1 lab=VDD}
 C {lab_pin.sym} 140 -120 0 0 {name=l2 sig_type=std_logic lab=0}
 C {pmos4.sym} 120 -350 0 0 {name=M2 model=p w=WP l=LLP m=1 net_name=true}
 C {nmos4.sym} 120 -170 0 0 {name=M1 model=n w=WN l=LLN m=1 net_name=true}
-C {lab_pin.sym} 140 -170 0 1 {name=l3 sig_type=std_logic lab=0}
-C {lab_pin.sym} 140 -350 0 1 {name=l4 sig_type=std_logic lab=VDD}
+C {lab_pin.sym} 200 -170 0 1 {name=l3 sig_type=std_logic lab=0}
+C {lab_pin.sym} 200 -350 0 1 {name=l4 sig_type=std_logic lab=VDD}
 C {title.sym} 160 -30 0 0 {name=l5 author="Stefan Schippers"}
 C {res.sym} 210 -230 1 0 {name=R1
-value=1k
+value=10
 footprint=1206
 device=resistor
 m=1}
 C {lab_pin.sym} 140 -220 0 1 {name=l6 sig_type=std_logic lab=D}
 C {lab_pin.sym} 80 -320 0 1 {name=l7 sig_type=std_logic lab=A}
 C {ammeter.sym} 140 -260 0 0 {name=V1}
+C {ammeter.sym} 300 -230 3 0 {name=Vmeas savecurrent=true}