diff --git a/src/save.c b/src/save.c
index 85c296c1..3cf60b50 100644
--- a/src/save.c
+++ b/src/save.c
@@ -1551,18 +1551,20 @@ int raw_get_pos(const char *node, double value, int dset, int from_start, int to
     if(idx >= 0) {
       double vx;
       int start, end;
+      int lastpoint = raw->npoints[dset] - 1;
 
       start = from_start >= 0 ? from_start : 0;
-      end = to_end >= 0 ? to_end : raw->npoints[dset] - 1;
+      end = to_end >= 0 ? to_end : lastpoint;
+      if(start > lastpoint) start = lastpoint;
+      if(end > lastpoint) end = lastpoint;
       double vstart = get_raw_value(dset, idx, start);
       double vend = get_raw_value(dset, idx, end);
       int sign = (vend > vstart) ? 1 : -1;
-      if(start >= end) start = end;
       if( sign * value >= sign * vstart && sign * value <= sign * vend) {
         while(1) {
           x = (start + end ) / 2;
           vx = get_raw_value(dset, idx, x);
-          if(end - start <= 1) break;
+          if(abs(end - start) <= 1) break;
           if( sign * vx > sign * value) end = x;
           else start = x;
         }
diff --git a/xschem_library/examples/test_backannotated_subckt.sch b/xschem_library/examples/test_backannotated_subckt.sch
index d6603ea8..5e92aa0b 100644
--- a/xschem_library/examples/test_backannotated_subckt.sch
+++ b/xschem_library/examples/test_backannotated_subckt.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.6 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -24,6 +24,28 @@ K {}
 V {}
 S {}
 E {}
+B 2 680 -520 1290 -250 {flags=graph
+y1=0
+y2=5
+ypos1=0
+ypos2=2
+divy=5
+subdivy=1
+unity=1
+x1=0
+x2=5e-08
+divx=5
+subdivx=1
+xlabmag=1.0
+ylabmag=1.0
+node="in
+out"
+color="4 7"
+dataset=-1
+unitx=1
+logx=0
+logy=0
+}
 T {To run this example a 'calc_rc' procedure must be defined. 
 I have embedded below procedure in title instance so
 it will be defined on load/drawing
@@ -31,13 +53,13 @@ Descend into the symbol ('i' key) and see how it is used in the 'format'
 attribute to calculate "Res" and "Cap" subcircuit parameters from W and L
 instance parameters.
 Tcl scripts can be loaded in xcshemrc by appending a tcl file name to variable
-'tcl_files'.} 30 -420 2 1 0.5 0.5 {layer=8 }
+'tcl_files'.} 20 -520 2 1 0.5 0.5 {layer=8 }
 T {proc calc_rc \{ L W \} \{
  if \{[catch \{expr 1200*$L/$W\} res]\} \{set res -1\}
  if \{[catch \{expr 1e-3*$W*$L\} cap]\} \{set cap -1\}
  return "Res=$res Cap=$cap"
-\} } 260 -400 0 0 0.4 0.4 { font=monospace}
-T {Dynamic calculation of subcircuit parameters} 70 -760 0 0 0.8 0.8 {}
+\} } 10 -500 0 0 0.4 0.4 { font=monospace}
+T {Dynamic calculation of subcircuit parameters} 30 -840 0 0 0.8 0.8 {}
 T {Title symbol has embedded TCL command
 define calc_rc} 330 -110 0 0 0.4 0.4 { layer=6}
 N 140 -130 140 -100 { lab=0}
@@ -52,7 +74,7 @@ if \{ [info commands calc_rc] eq \{\} \} \{
     proc calc_rc \{ L W \} \{
      if \{[catch \{expr 1200*$L/$W\} res]\} \{set res -1\}
      if \{[catch \{expr 1e-3*$W*$L\} cap]\} \{set cap -1\}
-     return \\"list Res=$res Cap=$cap\\"
+     return \\"Res=$res Cap=$cap\\"
     \}
     puts [info body calc_rc]
     puts \{############\}
@@ -64,12 +86,17 @@ C {lab_pin.sym} 140 -100 0 0 {name=l2 sig_type=std_logic lab=0}
 C {lab_pin.sym} 160 -210 0 1 {name=p3 lab=IN}
 C {rcline.sym} 530 -170 0 0 {name=x1 L=1e-4 W=0.5e-6
 }
-C {code_shown.sym} 890 -190 0 0 {name=STIMULI
+C {code_shown.sym} 830 -190 0 0 {name=STIMULI
 only_toplevel=false 
 
 value="
 .control
-tran 0.1n 50n
-plot in out
+  save all
+  tran 0.1n 50n
+  write test_backannotated_subckt.raw
 .endc
 "}
+C {launcher.sym} 1050 -230 0 0 {name=h5
+descr="load waves" 
+tclcommand="xschem raw_read $netlist_dir/test_backannotated_subckt.raw tran"
+}