diff --git a/xschem_library/xschem_simulator/segment.sym b/xschem_library/xschem_simulator/segment.sym
index 29a9ec29..ed0cdbb1 100644
--- a/xschem_library/xschem_simulator/segment.sym
+++ b/xschem_library/xschem_simulator/segment.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.6 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -27,4 +27,4 @@ V {}
 S {}
 E {}
 B 5 -0.3125 39.6875 0.3125 40.3125 {name=p dir=in}
-P 1 7 0 40 -40 0 -520 0 -560 40 -520 80 -40 80 0 40 {fill=true}
+P 1 7 0 40 -40 0 -520 0 -560 40 -520 80 -40 80 0 40 {fill=full}
diff --git a/xschem_library/xschem_simulator/simulate_ff.sch b/xschem_library/xschem_simulator/simulate_ff.sch
index 773a4ece..aa469f40 100644
--- a/xschem_library/xschem_simulator/simulate_ff.sch
+++ b/xschem_library/xschem_simulator/simulate_ff.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.5 file_version=1.2
+v {xschem version=3.4.6 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -42,7 +42,7 @@ L 4 1750 -1530 1750 -1520 {}
 L 4 1750 -1530 1770 -1520 {}
 L 4 1750 -1510 1770 -1520 {}
 L 4 1750 -1520 1750 -1510 {}
-B 12 3920 -2840 4640 -1540 {}
+B 12 3920 -2840 4640 -1540 {fill=full}
 P 5 9 1800 -300 1800 -220 1790 -230 1810 -180 1830 -230 1820 -220 1820 -300 1810 -290 1800 -300 {fill=true}
 T {7 Segment Display driver
 and base-10 counter} 1540 -3130 0 0 2.5 2.5 {}