This tells XSCHEM that for SPICE netlist this component will be completely ignored.
-This tells XSCHEM that for Verilog netlist this component will be completely ignored.
-This tells XSCHEM that for VHDL netlist this component will be completely ignored.
+These 4 attributes tell XSCHEM to ignore completely the instance in the respective netlist formats. + Allowed values for these attributes are true (or open), false and + short + If short is specified the instance will short together all its pins. For this to work + only one of the nets connected to the symbol may have a net label attached to it. All other nets will take this name. + If more labeled nets connect to the shorted symbol a net short error is reported. + Shorted instances are displayed in the pin color (red) layer. See in below image the upper netname of R1 + is VDD.
+
+ Disabled components (spice_ignore=true or spice_ignore=open) are displayed in grey.
+
+
+ This attribute works in the same way as above attributes, may take the values + true (or open), false or short, and + will affect the specific instance behaviour in the same way, but only if tcl variable + lvs_ignore is set to 1. This can be done in the Simulation menu: + Set 'lvs_ignore' variable. If this lvs_ignore is set on the instance + it will be shorted / ignored or kept as is depending on its lvs_ignore attribute + and will be effective in all netlising formats. This is mostly used to modify the produced netlist + automatically when doing schematic vs layout (LVS) comparison.
+ +By using the *_ignore attributes you can modify the circuit depending on the value of a tcl variable:
+
+ just set the attribute to something like:
+ spice_ignore="tcleval([if {$IGNORE == 1} {return {true}} else {return {false}}])"
+ or:
+ spice_ignore="tcleval([if {$IGNORE == 1} {return {short}} else {return {false}}])" These 3 attributes tell XSCHEM to ignore completely the symbol in the respective netlist formats.
+These 4 attributes tell XSCHEM to ignore completely all instances of the symbol in the respective netlist formats.
+ Allowed values for these attributes are true (or open), false and
+ short
+ If short is specified all symbol instances will short together all their pins. For this to work
+ only one of the nets connected to the symbol may have a net label attached to it. All other nets will take this name.
+ If more labeled nets connect to the shorted symbol a net short error is reported.
+ Shorted symbol instances are displayed in the pin color (red) layer. See some images in the
+ component properties man page when describing the same instance
+ based attributes.
+ Disabled symbols (spice_ignore=true or spice_ignore=open) are displayed in grey.
This attribute works in the same way as above attributes, may take the values + true (or open), false or short, and + will affect the symbol behaviour in the same way, but only if tcl variable + lvs_ignore is set to 1. This can be done in the Simulation menu: + Set 'lvs_ignore' variable. If this lvs_ignore is set on the symbol + it will be shorted / ignored or kept as is depending on its lvs_ignore attribute + and will be effective in all netlising formats. This is mostly used to modify the produced netlist + automatically when doing schematic vs layout (LVS) comparison.
+ +These 3 attributes will avoid XSCHEM to descend into the schematic representation of the symbol - (if there is one) when building the respective netlist format. For example, if an analog block - has a schematic (.sch) file describing the circuit that is meaningless when doing a VHDL netlist, - we can use a vhdl_stop=true attribute to avoid descending into the schematic. - Only the global property of the schematic will be netlisted. This allows to insert some - behavioral VHDL code in the global schematic property that describes the block in a way - the VHDL simulator can understand.
+These 4 attributes will avoid XSCHEM to descend into the schematic representation of the symbol + (if there is one) when building the respective netlist format. For example, if an analog block + has a schematic (.sch) file describing the circuit that is meaningless when doing a VHDL netlist, + we can use a vhdl_stop=true attribute to avoid descending into the schematic. + Only the global property of the schematic will be netlisted. This allows to insert some + behavioral VHDL code in the global schematic property that describes the block in a way + the VHDL simulator can understand.