diff --git a/src/parselabel.l b/src/parselabel.l
index aecdeea1..6c19a9cb 100644
--- a/src/parselabel.l
+++ b/src/parselabel.l
@@ -146,13 +146,13 @@ LAB [-a-zA-Z_%$~"#/\\<>]
   /* includes numbers */
 LAB_NUM [-a-zA-Z_%$~"#/\\<>0-9]
   /* includes numbers and space and *+(). */
-IDX_LAB_NUM_SP [-a-zA-Z_%$~"#/\\<> \t0-9*+().]
+IDX_LAB_NUM_SP [-a-zA-Z_%$~"#/\\<> \t\n0-9*+().]
   /* identifier, may start with a number */
 IDX_ID_N ({LAB_NUM}+({IDX_LAB_NUM_SP}*{LAB_NUM})*)
   /* identifier, not starting with a number */
 IDX_ID (("("|{LAB})+{IDX_LAB_NUM_SP}*)
   /* includes numbers and space and +().  and :*/
-LAB_NUM_SP [-a-zA-Z_%$~"#:/\\<> \t0-9+().]
+LAB_NUM_SP [-a-zA-Z_%$~"#:/\\<> \t\n0-9+().]
   /* identifier, may start with a number */
 ID_NUM ({LAB_NUM}+({LAB_NUM_SP}*{LAB_NUM})*)
   /* identifier, not starting with a number */
diff --git a/xschem_library/pcb/74ls00.sym b/xschem_library/pcb/74ls00.sym
index da7f54b2..a80fc1b9 100644
--- a/xschem_library/pcb/74ls00.sym
+++ b/xschem_library/pcb/74ls00.sym
@@ -1,10 +1,23 @@
-v {xschem version=2.9.5_RC6 file_version=1.1}
-G {type=nand
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=nand
 format="@name @pinlist @value"
 verilog_format="nand #(@risedel , @falldel ) @name ( @#2 , @#0 , @#1 );"
+risedel=100
+falldel=200 
+
 tedax_format="footprint @name @footprint
-device @name @symname"
-template="name=U1 footprint=\\"dip(14)\\" risedel=100 falldel=200 numslots=4 power=VCC ground=GND"
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=U1 footprint=\\"dip(14)\\" 
+numslots=4 
+power=VCC 
+ground=GND"
+
 extra="power ground"
 extra_pinnumber="14 7"}
 V {}