diff --git a/src/callback.c b/src/callback.c
index f95fdaea..dce70d83 100644
--- a/src/callback.c
+++ b/src/callback.c
@@ -87,7 +87,14 @@ void redraw_w_a_l_r_p_rubbers(void)
   if(xctx->ui_state & STARTWIRE) {
     if(xctx->constr_mv == 1) xctx->mousey_snap = xctx->my_double_save;
     if(xctx->constr_mv == 2) xctx->mousex_snap = xctx->mx_double_save;
-    new_wire(RUBBER, xctx->mousex_snap, xctx->mousey_snap);
+    if(tclgetboolvar("orthogonal_wiring")) {
+      new_wire(RUBBER|CLEAR, xctx->mousex_snap, xctx->mousey_snap);
+      int tmp_x2 = xctx->nl_x2 - xctx->nl_x1, tmp_y2 = xctx->nl_y2 - xctx->nl_y1;
+      if(tmp_x2*tmp_x2 > tmp_y2*tmp_y2) xctx->manhattan_lines = 1;
+      else xctx->manhattan_lines = 2;
+      new_wire(RUBBER, xctx->mousex_snap, xctx->mousey_snap);
+    }
+    else new_wire(RUBBER, xctx->mousex_snap, xctx->mousey_snap);
   }
   if(xctx->ui_state & STARTARC) {
     if(xctx->constr_mv == 1) xctx->mousey_snap = xctx->my_double_save;
@@ -3323,6 +3330,16 @@ int rstate; /* (reduced state, without ShiftMask) */
     place_net_label(0);
     break;
    }
+   if(key=='L' && rstate == 0) {                         /* toggle orthogonal routing */
+    if(tclgetboolvar("orthogonal_wiring")){
+      tclsetboolvar("orthogonal_wiring", 0);
+    } else {
+      tclsetboolvar("orthogonal_wiring", 1);
+    }
+    xctx->manhattan_lines = 0;
+    redraw_w_a_l_r_p_rubbers();
+    break;
+   }
    if(key=='F' && rstate == 0)                     /* flip */
    {
     if(xctx->ui_state & STARTMOVE) move_objects(FLIP,0,0,0);
diff --git a/src/xschem.tcl b/src/xschem.tcl
index 8d0b32e5..1e40e473 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -7521,7 +7521,7 @@ set tctx::global_list {
   PDK_ROOT PDK SKYWATER_MODELS SKYWATER_STDCELLS 
   INITIALINSTDIR INITIALLOADDIR INITIALPROPDIR INITIALTEXTDIR XSCHEM_LIBRARY_PATH
   add_all_windows_drives auto_hilight auto_hilight_graph_nodes autofocus_mainwindow
-  autotrim_wires infix_wire bespice_listen_port big_grid_points bus_replacement_char cadgrid cadlayers
+  autotrim_wires infix_wire orthogonal_wiring bespice_listen_port big_grid_points bus_replacement_char cadgrid cadlayers
   cadsnap cairo_font_name cairo_font_scale change_lw color_ps tctx::colors compare_sch constr_mv
   copy_cell crosshair_layer custom_label_prefix custom_token dark_colors dark_colorscheme
   dark_gui_colorscheme delay_flag  dim_bg dim_value disable_unique_names
@@ -7942,7 +7942,7 @@ proc build_widgets { {topwin {} } } {
   global netlist_show flat_netlist split_files compare_sch intuitive_interface
   global draw_grid big_grid_points sym_txt change_lw incr_hilight symbol_width
   global cadsnap cadgrid draw_window toolbar_visible hide_symbols undo_type
-  global disable_unique_names persistent_command autotrim_wires infix_wire en_hilight_conn_inst
+  global disable_unique_names persistent_command autotrim_wires infix_wire orthogonal_wiring en_hilight_conn_inst
   global local_netlist_dir editor netlist_type netlist_dir spiceprefix initial_geometry
   if { $dark_gui_colorscheme} {
     set selectcolor white
@@ -8067,6 +8067,8 @@ proc build_widgets { {topwin {} } } {
      -selectcolor $selectcolor  -accelerator Y 
   $topwin.menubar.option add checkbutton -label "Enable infix-wire" -variable infix_wire \
      -selectcolor $selectcolor
+  $topwin.menubar.option add checkbutton -label "Enable orthogonal wiring mode" -variable orthogonal_wiring \
+     -selectcolor $selectcolor  -accelerator Shift+L
   $topwin.menubar.option add checkbutton -label "Unsel. partial sel. wires after stretch move" \
      -selectcolor $selectcolor -variable unselect_partial_sel_wires
 
@@ -8998,6 +9000,7 @@ set_ne persistent_command 0
 set_ne intuitive_interface 1
 set_ne autotrim_wires 0
 set_ne infix_wire 0
+set_ne orthogonal_wiring 1
 set_ne compare_sch 0
 set_ne disable_unique_names 0
 set_ne sym_txt 1
diff --git a/src/xschemrc b/src/xschemrc
index fa6f7363..fc15f538 100644
--- a/src/xschemrc
+++ b/src/xschemrc
@@ -226,6 +226,12 @@
 #### default: 0
 # set infix_wire 1
 
+#### wires are drawn in free-form mode with this mode enabled (default).
+#### if set to 0, wires drawn on the schematic will no longer strictly
+#### follow orthogonal routes to connect two distinct points toegther.
+#### default: 1
+# set orthogonal_wiring 0
+
 #### if set to 1 automatically join/trim wires while editing
 #### this may slow down on rally big designs. Can be disabled via menu 
 #### default: 0