diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index d250eb93..701ff5fb 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -317,8 +317,9 @@ int global_spice_netlist(int global)  /* netlister driver */
  if(!stat(top_symbol_name, &buf)) { /* if top level has a symbol use the symbol for pin ordering */
    dbg(1, "found top level symbol %s\n", top_symbol_name);
    load_sym_def(top_symbol_name, NULL);
-   /* only use the symbol if it has pins */
-   if(xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
+   /* only use the symbol if it has pins and is a subcircuit */
+   if(!strcmp(xctx->sym[xctx->symbols - 1].type, "subcircuit") &&
+       xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
      fprintf(fd," ");
      print_spice_subckt_nodes(fd, xctx->symbols - 1);
      found_top_symbol = 1;
diff --git a/tests/xschemtest.tcl b/tests/xschemtest.tcl
index 5267944a..75435a8c 100644
--- a/tests/xschemtest.tcl
+++ b/tests/xschemtest.tcl
@@ -197,7 +197,7 @@ proc netlist_test {} {
     inst_sch_select.sch     spice       801962545
     test_bus_tap.sch        spice       181420586
     loading.sch             vhdl       2975204502
-    mos_power_ampli.sch     spice      4084823731
+    mos_power_ampli.sch     spice       475695942
     hierarchical_tedax.sch  tedax       998070173
     LCC_instances.sch       spice       696885230
     pcb_test1.sch           tedax      1925087189
diff --git a/xschem_library/examples/mos_power_ampli.sch b/xschem_library/examples/mos_power_ampli.sch
index a3a9c29b..53687df3 100644
--- a/xschem_library/examples/mos_power_ampli.sch
+++ b/xschem_library/examples/mos_power_ampli.sch
@@ -35,8 +35,8 @@ y1=-47
 y2=50
 divy=4
 subdivy=4
-x1=0.00823137
-x2=0.00892608
+x1=0.0227349
+x2=0.0233008
 divx=8
 subdivx=1
 dataset=0
@@ -54,8 +54,8 @@ y1=0
 y2=160
 divy=4
 subdivy=9
-x1=0.00823137
-x2=0.00892608
+x1=0.0227349
+x2=0.0233008
 divx=8
 subdivx=9
 dataset=0
@@ -72,8 +72,8 @@ y1=-0.19
 y2=160
 divy=4
 subdivy=9
-x1=0.00823137
-x2=0.00892608
+x1=0.0227349
+x2=0.0233008
 divx=8
 subdivx=9
 dataset=0
@@ -203,11 +203,11 @@ C {nmos3.sym} 1090 -530 0 0 {name=xm2 model=irf540 m=1
 program=evince
 url="https://www.vishay.com/docs/91021/irf540.pdf"
  net_name=true}
-C {res.sym} 960 -500 0 1 {name=R7 m=1 value=190 net_name=true}
+C {res.sym} 960 -500 0 1 {name=R7 m=1 value=320 net_name=true}
 C {nmos3.sym} 1090 -850 0 0 {name=xm1 model=irf540 m=1
 program=evince
 url="https://www.vishay.com/docs/91021/irf540.pdf" net_name=true}
-C {res.sym} 960 -820 0 1 {name=R0 m=1 value=190 net_name=true}
+C {res.sym} 960 -820 0 1 {name=R0 m=1 value=320 net_name=true}
 C {lab_wire.sym} 880 -530 0 0 {name=l8 lab=GB}
 C {res.sym} 340 -1140 0 1 {name=R2 m=1 value=50 net_name=true}
 C {res.sym} 180 -1140 0 1 {name=R3 m=1 value=50 net_name=true}
@@ -268,7 +268,7 @@ rload out 0 4
 *.probe dc v(plus,vdc)
 "}
 C {lab_wire.sym} 920 -850 0 0 {name=l1 lab=GA}
-C {res.sym} 800 -530 1 1 {name=R11 m=1 value=1300 net_name=true
+C {res.sym} 800 -530 1 1 {name=R11 m=1 value=400 net_name=true
 hide_texts=true}
 C {pnp.sym} 540 -580 0 0 {name=Q8 model=q2n2907p area=1 net_name=true}
 C {capa.sym} 1240 -1020 0 0 {name=C12 m=1 value="40u" net_name=true}
@@ -280,17 +280,17 @@ url="http://www.futurlec.com/Datasheet/Diodes/1N746-1N759.pdf" net_name=true}
 C {res.sym} 690 -850 0 1 {name=R14 m=1 value=4k net_name=true}
 C {pnp.sym} 820 -900 0 0 {name=Q11 model=q2n2907p area=1 net_name=true}
 C {res.sym} 690 -940 0 1 {name=R15 m=1 value=4k net_name=true}
-C {res.sym} 260 -510 0 1 {name=R5 m=1 value=120 net_name=true}
-C {res.sym} 260 -450 0 1 {name=R6 m=1 value=120 net_name=true}
+C {res.sym} 260 -510 0 1 {name=R5 m=1 value=40 net_name=true}
+C {res.sym} 260 -450 0 1 {name=R6 m=1 value=40 net_name=true}
 C {zener.sym} 150 -270 2 0 {name=D2 model=d1n755 area=1
 url="http://www.futurlec.com/Datasheet/Diodes/1N746-1N759.pdf"
  net_name=true}
 C {npn.sym} 240 -300 0 0 {name=Q3 model=q2n2222 area=1 net_name=true}
 C {res.sym} 150 -330 0 1 {name=R1 m=1 value=10k net_name=true}
 C {lab_pin.sym} 150 -360 0 0 {name=p7 lab=VPP}
-C {res.sym} 260 -210 0 1 {name=R10 m=1 value=170 net_name=true}
+C {res.sym} 260 -210 0 1 {name=R10 m=1 value=300 net_name=true}
 C {capa.sym} 50 -270 0 0 {name=C3 m=1 value=100n net_name=true}
-C {res.sym} 560 -700 0 1 {name=R12 m=1 value=1300 net_name=true}
+C {res.sym} 560 -700 0 1 {name=R12 m=1 value=400 net_name=true}
 C {lab_pin.sym} 690 -890 0 0 {name=p12 lab=B1}
 C {lab_pin.sym} 340 -550 0 1 {name=p13 lab=E9}
 C {lab_pin.sym} 560 -530 0 0 {name=p19 lab=C8}
@@ -465,3 +465,7 @@ C {ngspice_get_expr.sym} 1130 -860 0 0 {name=r22
 node="[ngspice::get_current \{xm1.rd[i]\}]" 
 descr = current
 }
+C {ngspice_get_expr.sym} 610 -830 0 1 {name=r20 
+node="[format %.4g [expr [ngspice::get_current \{q6[ic]\}] / [ngspice::get_current \{q6[ib]\}] ] ]"
+descr = beta
+}
diff --git a/xschem_library/examples/poweramp.sch b/xschem_library/examples/poweramp.sch
index 4ad3b99c..11e30b6d 100644
--- a/xschem_library/examples/poweramp.sch
+++ b/xschem_library/examples/poweramp.sch
@@ -38,8 +38,8 @@ B 2 1200 -500 1880 -310 {flags=graph
 y1 = -0.0059
 y2 = 11
 divy = 6
-x1=0.00562909
-x2=0.0165959
+x1=0.0227673
+x2=0.0231289
 divx=10
 node="i(v.x1.vu)
 i(v.x0.vu)
@@ -52,8 +52,8 @@ B 2 1200 -830 1880 -520 {flags=graph
 y1 = -49
 y2 = 58
 divy = 12
-x1=0.00562909
-x2=0.0165959
+x1=0.0227673
+x2=0.0231289
 divx=10
 node="outp
 outm
@@ -68,8 +68,8 @@ B 2 1200 -1020 1880 -830 {flags=graph
 y1 = 0
 y2 = 830
 divy = 6
-x1=0.00562909
-x2=0.0165959
+x1=0.0227673
+x2=0.0231289
 divx=10
 
 
@@ -82,8 +82,8 @@ B 2 1200 -310 1880 -120 {flags=graph
 y1 = 0
 y2 = 840
 divy = 6
-x1=0.00562909
-x2=0.0165959
+x1=0.0227673
+x2=0.0231289
 divx=10
 
 
@@ -185,8 +185,8 @@ N 240 -320 240 -220 { lab=INX}
 N 160 -1220 180 -1220 {lab=#net3}
 N 160 -1060 180 -1060 {lab=#net4}
 N 70 -1140 180 -1140 {lab=#net5}
-C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc 50 pwl 0 0 1m 50"}
-C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc 50 pwl 0 0 1m 50"}
+C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc VPP pwl 0 0 1m VPP"}
+C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc VPP pwl 0 0 1m VPP"}
 C {lab_pin.sym} 310 -1220 0 1 {name=p5 lab=VPP}
 C {lab_pin.sym} 310 -1060 0 1 {name=p6 lab=VNN}
 C {lab_pin.sym} 310 -1140 0 1 {name=p3 lab=VSS}
@@ -199,9 +199,9 @@ C {lab_pin.sym} 700 -1200 0 1 {name=p32 lab=REFP}
 C {capa.sym} 260 -1100 0 0 {name=C3 m=1 value="100u"}
 C {res.sym} 130 -1220 1 1 {name=R11 m=1 value=0.3}
 C {res.sym} 130 -1060 1 1 {name=R9 m=1 value=0.3}
-C {res.sym} 550 -920 0 1 {name=R19 m=1 value='100k'
+C {res.sym} 550 -920 0 1 {name=R19 m=1 value=50k
 }
-C {res.sym} 550 -860 0 1 {name=R0 m=1 value="'100k/gain'"}
+C {res.sym} 550 -860 0 1 {name=R0 m=1 value="'50k/gain'"}
 C {lab_pin.sym} 550 -750 0 0 {name=p108 lab=IN}
 C {mos_power_ampli.sym} 500 -660 0 0 {name=x1}
 C {lab_pin.sym} 350 -640 0 0 {name=p2 lab=VPP}
@@ -210,9 +210,9 @@ C {lab_pin.sym} 860 -700 0 1 {name=p9 lab=OUTM}
 C {mos_power_ampli.sym} 500 -200 0 0 {name=x0}
 C {lab_pin.sym} 350 -180 0 0 {name=p12 lab=VPP}
 C {lab_pin.sym} 350 -160 0 0 {name=p13 lab=VNN}
-C {res.sym} 240 -350 0 1 {name=R6 m=1 value=100k}
+C {res.sym} 240 -350 0 1 {name=R6 m=1 value=50k}
 C {lab_pin.sym} 240 -400 0 0 {name=p7 lab=VPP}
-C {res.sym} 260 -160 0 1 {name=R7 m=1 value=100k}
+C {res.sym} 260 -160 0 1 {name=R7 m=1 value=50k}
 C {lab_pin.sym} 260 -110 0 0 {name=p15 lab=VSS}
 C {lab_pin.sym} 500 -1070 0 0 {name=p20 lab=VSS}
 C {lab_pin.sym} 540 -1110 0 0 {name=p21 lab=IN}
@@ -226,17 +226,17 @@ C {lab_pin.sym} 550 -290 0 0 {name=p11 lab=VSS}
 C {capa.sym} 550 -340 0 0 {name=C6 m=1 value="100n ; ic=0"}
 C {lab_pin.sym} 350 -200 0 0 {name=p28 lab=VSS}
 C {lab_pin.sym} 350 -660 0 0 {name=p1 lab=VSS}
-C {res.sym} 550 -460 0 1 {name=R2 m=1 value='100k'}
-C {res.sym} 550 -400 0 1 {name=R3 m=1 value="'100k/(gain-2)'"}
+C {res.sym} 550 -460 0 1 {name=R2 m=1 value=50k}
+C {res.sym} 550 -400 0 1 {name=R3 m=1 value="'50k/(gain-2)'"}
 C {vsource.sym} 870 -1140 0 0 {name=V3 
 xvalue="dc 0 pulse -.1 .1 1m .1u .1u 10.1u 20u" 
 value="dc 0 sin 0 1 \{frequ\} 1m"
 }
-C {res.sym} 240 -810 0 1 {name=R4 m=1 value=100k}
+C {res.sym} 240 -810 0 1 {name=R4 m=1 value=50k}
 C {lab_pin.sym} 240 -860 0 0 {name=p18 lab=VPP}
-C {res.sym} 260 -620 0 1 {name=R5 m=1 value=100k}
+C {res.sym} 260 -620 0 1 {name=R5 m=1 value=50k}
 C {lab_pin.sym} 260 -570 0 0 {name=p10 lab=VSS}
-C {res.sym} 400 -950 0 1 {name=R8 m=1 value=100k}
+C {res.sym} 400 -950 0 1 {name=R8 m=1 value=50k}
 C {capa.sym} 170 -220 1 0 {name=C4 m=1 value="100n ; ic=0"}
 C {lab_pin.sym} 140 -220 0 0 {name=p0 lab=IN}
 C {capa.sym} 150 -680 1 0 {name=C1 m=1 value="100n ; ic=0"}
@@ -244,7 +244,7 @@ C {lab_pin.sym} 120 -680 0 0 {name=p17 lab=VSS}
 C {lab_pin.sym} 240 -710 0 0 {name=p22 lab=VSSX}
 C {res.sym} 920 -1200 1 1 {name=R10 m=1 value=2}
 C {lab_pin.sym} 400 -1000 0 0 {name=p24 lab=VPP}
-C {res.sym} 400 -490 0 1 {name=R13 m=1 value=100k}
+C {res.sym} 400 -490 0 1 {name=R13 m=1 value=50k}
 C {lab_pin.sym} 400 -540 0 0 {name=p16 lab=VPP}
 C {vsource.sym} 870 -1080 0 0 {name=Vin value=0 xvalue="pwl 0 .1 1m .1 1.01m 0"
 }
@@ -338,6 +338,7 @@ spice_ignore=0
 value="
 .option ITL4=20000 ITL5=0
 vvss vss 0 dc 0 
+.param VPP=50
 .temp 30
 .param frequ=5k
 .param gain=45
@@ -351,7 +352,7 @@ vvss vss 0 dc 0
 save all
 op
 write poweramp_op.raw
-tran  8e-7 0.07 uic
+tran  8e-7 0.025 uic
 * .FOUR 20k v(outm,outp)
 * .probe i(*) 
 plot outp outm
diff --git a/xschem_library/logic/iv.sym b/xschem_library/logic/iv.sym
index a767cc43..3abcc7ac 100644
--- a/xschem_library/logic/iv.sym
+++ b/xschem_library/logic/iv.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -19,11 +19,12 @@ v {xschem version=3.4.4 file_version=1.2
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 }
-G {type=gate
+G {}
+K {type=gate
 vhdl_stop=true
-verilog_format = "assign #@del @@Y = ~ @@A[max:0] ;"
-vhdl_format = " @@Y <= not @@A[max:0] after @del ps ;"
-format="@name [ @@A[max:0]  ] @@Y inv"
+verilog_format = "assign #@del @@Y = ~ @@A ;"
+vhdl_format = " @@Y <= not @@A after @del ps ;"
+format="@name [ @@A  ] @@Y inv"
 template="name=x1 delay=\\"70 ps\\" del=70"
 generic_type="delay=time"
 }
@@ -36,7 +37,7 @@ L 4 -25 -20 15 0 {}
 L 4 -25 20 15 0 {}
 L 4 25 0 40 0 {}
 B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out verilog_type=wire}
-B 5 -42.5 -2.5 -37.5 2.5 {name=A[max:0] dir=in}
+B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in}
 A 4 20 0 5 180 360 {}
 T {@name} -23.75 -5 0 0 0.2 0.2 {}
 T {IV} -2.8125 -28.75 0 0 0.3 0.3 {}