From 394db224d18b52b1827cd3e87898ab457761eb6d Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Tue, 6 Jun 2023 15:22:45 +0200
Subject: [PATCH] added global tcl variable `lvs_ignore` that can be used to
 enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short`
 while netlisting, added `test_lvs_ignore.sch` example

---
 src/actions.c                                 |  18 +++-
 src/draw.c                                    |  37 +++++--
 src/hilight.c                                 |   1 +
 src/netlist.c                                 |  58 +++++++---
 src/spice_netlist.c                           |  27 ++---
 src/tedax_netlist.c                           |  11 +-
 src/token.c                                   |   1 +
 src/verilog_netlist.c                         |  51 +++------
 src/vhdl_netlist.c                            |  66 ++++--------
 src/xschem.h                                  |   8 ++
 src/xschem.tcl                                |   3 +
 xschem_library/devices/short.sym              |   2 +-
 xschem_library/examples/0_examples_top.sch    |  61 +++++------
 xschem_library/examples/test_lvs_ignore.sch   | 102 ++++++++++++++++++
 xschem_library/examples/test_lvs_ignore.sym   |  11 ++
 xschem_library/examples/test_short_option.sch |  45 ++++----
 16 files changed, 320 insertions(+), 182 deletions(-)
 create mode 100644 xschem_library/examples/test_lvs_ignore.sch
 create mode 100644 xschem_library/examples/test_lvs_ignore.sym

diff --git a/src/actions.c b/src/actions.c
index 0ca770f7..c32f54b6 100644
--- a/src/actions.c
+++ b/src/actions.c
@@ -704,14 +704,19 @@ int set_sym_flags(xSymbol *sym)
   if(!strcmp(get_tok_value(sym->prop_ptr,"tedax_ignore",0), "true"))
        sym->flags |= TEDAX_IGNORE_INST;
 
+  if(!strcmp(get_tok_value(sym->prop_ptr,"lvs_ignore",0), "short"))
+       sym->flags |= LVS_IGNORE_SHORT;
+
+  if(!strcmp(get_tok_value(sym->prop_ptr,"lvs_ignore",0), "open"))
+       sym->flags |= LVS_IGNORE_OPEN;
+  dbg(1, "set_sym_flags: inst %s flags=%d\n", sym->name, sym->flags);
   return 0;
 }
 
 int set_inst_flags(xInstance *inst)
 {
-  inst->flags=0;
+  inst->flags &= IGNORE_INST; /* do not clear IGNORE_INST bit, used in draw_symbol() */
   my_strdup2(_ALLOC_ID_, &inst->instname, get_tok_value(inst->prop_ptr, "name", 0));
-
   if(inst->ptr >=0) {
     char *type = xctx->sym[inst->ptr].type;
     int cond= type && IS_LABEL_SH_OR_PIN(type);
@@ -738,7 +743,15 @@ int set_inst_flags(xInstance *inst)
   if(!strcmp(get_tok_value(inst->prop_ptr,"highlight",0), "true"))
     inst->flags |= HILIGHT_CONN;
 
+  if(!strcmp(get_tok_value(inst->prop_ptr,"lvs_ignore",0), "open"))
+    inst->flags |= LVS_IGNORE_OPEN;
+
+  if(!strcmp(get_tok_value(inst->prop_ptr,"lvs_ignore",0), "short"))
+    inst->flags |= LVS_IGNORE_SHORT;
+
   inst->embed = !strcmp(get_tok_value(inst->prop_ptr, "embed", 2), "true");
+
+  dbg(1, "set_inst_flags: inst %s flags=%d\n", inst->instname, inst->flags);
   return 0;
 }
 
@@ -775,6 +788,7 @@ int set_text_flags(xText *t)
 void reset_flags(void)
 {
   int i;
+  dbg(1, "reset_flags()\n");
   for(i = 0; i < xctx->instances; i++) {
     set_inst_flags(&xctx->inst[i]);
   }     
diff --git a/src/draw.c b/src/draw.c
index 1d195a16..9e4fb3ae 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -431,13 +431,17 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
   register xSymbol *symptr;
   double angle;
   char *type;
+  int lvs_ignore = 0;
   #if HAS_CAIRO==1
   const char *textfont;
   #endif
 
+  lvs_ignore=tclgetboolvar("lvs_ignore");
   if(xctx->inst[n].ptr == -1) return;
   if(layer == 0) { 
     char *type = xctx->sym[xctx->inst[n].ptr].type;
+    
+    xctx->inst[n].flags &= ~IGNORE_INST; /* clear bit */
     if( type && strcmp(type, "launcher") && strcmp(type, "logo") &&
         strcmp(type, "probe") &&
         strcmp(type, "architecture") && strcmp(type, "noconn")) {
@@ -472,20 +476,32 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
               (xctx->inst[n].flags & TEDAX_IGNORE_INST) ||
               (xctx->sym[xctx->inst[n].ptr].flags & TEDAX_IGNORE_INST)
             )
+          ) ||
+          (
+            lvs_ignore &&
+            (
+              (xctx->inst[n].flags & LVS_IGNORE_OPEN) ||
+              (xctx->sym[xctx->inst[n].ptr].flags & LVS_IGNORE_OPEN)
+            )
           )
-  
         ) {
          xctx->inst[n].flags |= IGNORE_INST; /* *_IGNORE_INST in current netlisting mode as evaluated above */
-      } else {
-         xctx->inst[n].flags &= ~IGNORE_INST;
       }
     }
   }
-  if(xctx->inst[n].flags & IGNORE_INST) {
+  if(lvs_ignore &&
+    ( (xctx->inst[n].flags & LVS_IGNORE_SHORT) ||
+      (xctx->sym[xctx->inst[n].ptr].flags & LVS_IGNORE_SHORT)) ) {
+    c = PINLAYER;
+    what = NOW;
+    disabled = 2;
+  }
+  else if(xctx->inst[n].flags & IGNORE_INST) {
     c = GRIDLAYER;
     what = NOW;
     disabled = 1;
   }
+
   if( (layer != PINLAYER && !xctx->enable_layer[layer]) ) return;
   if(!has_x) return;
   if( (xctx->inst[n].flags & HIDE_INST) ||
@@ -530,7 +546,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
       xctx->inst[n].flags&=~1;
     }
     if(hide) {
-      int color = disabled ? GRIDLAYER : SYMLAYER;
+      int color = (disabled==1) ? GRIDLAYER : (disabled == 2) ? PINLAYER : SYMLAYER;
       drawrect(color, NOW, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2, 2);
     }
   } else if(xctx->inst[n].flags&1) {
@@ -550,7 +566,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
     {
       int dash;
       line = &(symptr->line[layer])[j];
-      dash = disabled ? 3 : line->dash;
+      dash = (disabled == 1) ? 3 : line->dash;
       ROTATION(rot, flip, 0.0,0.0,line->x1,line->y1,x1,y1);
       ROTATION(rot, flip, 0.0,0.0,line->x2,line->y2,x2,y2);
       ORDER(x1,y1,x2,y2);
@@ -563,7 +579,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
     {
       int dash;
       polygon = &(symptr->poly[layer])[j];
-      dash = disabled ? 3 : polygon->dash;
+      dash = (disabled == 1) ? 3 : polygon->dash;
       x = my_malloc(_ALLOC_ID_, sizeof(double) * polygon->points);
       y = my_malloc(_ALLOC_ID_, sizeof(double) * polygon->points);
       for(k=0;k<polygon->points; ++k) {
@@ -579,7 +595,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
     {
       int dash;
       arc = &(symptr->arc[layer])[j];
-      dash = disabled ? 3 : arc->dash;
+      dash = (disabled == 1) ? 3 : arc->dash;
       if(flip) {
         angle = 270.*rot+180.-arc->b-arc->a;
       } else {
@@ -598,7 +614,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
     {
       int dash;
       rect = &(symptr->rect[layer])[j];
-      dash = disabled ? 3 : rect->dash;
+      dash = (disabled == 1) ? 3 : rect->dash;
       ROTATION(rot, flip, 0.0,0.0,rect->x1,rect->y1,x1,y1);
       ROTATION(rot, flip, 0.0,0.0,rect->x2,rect->y2,x2,y2);
       #if HAS_CAIRO == 1
@@ -634,7 +650,8 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
       ROTATION(rot, flip, 0.0,0.0,text.x0,text.y0,x1,y1);
       textlayer = c;
       /* do not allow custom text color on hilighted instances */
-      if(disabled) textlayer = GRIDLAYER;
+      if(disabled == 1) textlayer = GRIDLAYER;
+      else if(disabled == 2) textlayer = PINLAYER;
       else if( xctx->inst[n].color == -10000) {
         textlayer = symptr->text[j].layer;
         if(xctx->only_probes) textlayer = GRIDLAYER;
diff --git a/src/hilight.c b/src/hilight.c
index 9137d06f..426a5aad 100644
--- a/src/hilight.c
+++ b/src/hilight.c
@@ -1741,6 +1741,7 @@ void hilight_net(int viewer)
    switch(xctx->sel_array[i].type) {
     case WIRE:
          /* sets xctx->hilight_nets=1 */
+     if(!xctx->wire[n].node) break;
      if(!bus_hilight_hash_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT_NOREPLACE)) {
        if(viewer == XSCHEM_GRAPH) {
          send_net_to_graph(&s, sim_is_xyce, xctx->wire[n].node);
diff --git a/src/netlist.c b/src/netlist.c
index 4bf7dfef..0729676c 100644
--- a/src/netlist.c
+++ b/src/netlist.c
@@ -23,6 +23,7 @@
 #include "xschem.h"
 
 static int for_netlist = 0;
+static int netlist_lvs_ignore = 0;
 static void instdelete(int n, int x, int y)
 {
   Instentry *saveptr, **prevptr;
@@ -401,6 +402,12 @@ void netlist_options(int i)
   }
   /* fprintf(errfp, "netlist_options(): bus_char=%s\n", str); */
 
+  str = get_tok_value(xctx->inst[i].prop_ptr, "lvs_ignore", 0);
+  if(str[0]) {
+    /* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
+    if(!strcmp(str, "true")) tclsetintvar("lvs_ignore", 1);
+    else tclsetintvar("lvs_.netlist", 0);
+  }
   str = get_tok_value(xctx->inst[i].prop_ptr, "lvs_netlist", 0);
   if(str[0]) {
     /* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
@@ -592,6 +599,7 @@ static void name_generics()
       if((generic_rects = (inst[i].ptr+ xctx->sym)->rects[GENERICLAYER]) > 0) {
         rects = (inst[i].ptr+ xctx->sym)->rects[PINLAYER];
         for (j=rects;j<rects+generic_rects; ++j) {
+          if(!inst[i].node) continue;
           if(inst[i].node[j]) continue; /* already named node */
           rct=(inst[i].ptr+ xctx->sym)->rect[GENERICLAYER];
           x0=(rct[j-rects].x1+rct[j-rects].x2)/2;
@@ -607,6 +615,7 @@ static void name_generics()
             int p = iptr->pin;
             int n = iptr->n;
             if(n == i) continue;
+            if(!inst[n].node) continue;
             if((iptr->x0==x0) && (iptr->y0==y0)) {
               if((inst[n].ptr+ xctx->sym)->type && inst[n].node[p] != NULL &&
                  !strcmp((inst[n].ptr+ xctx->sym)->type, "label")) {
@@ -662,6 +671,7 @@ static void set_inst_node(int i, int j, const char *node)
   int inst_mult;
   xRect *rect = (inst[i].ptr + xctx->sym)->rect[PINLAYER];
 
+  if(!inst[i].node) return;
   dbg(1, "set_inst_node(): inst %s pin %d <-- %s\n", inst[i].instname, j, node);
   expandlabel(inst[i].instname, &inst_mult);
   my_strdup(_ALLOC_ID_,  &inst[i].node[j], node);
@@ -697,7 +707,7 @@ static int name_attached_inst_to_net(int k, int sqx, int sqy)
     if(touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, x0, y0)) {
       if(!inst[n].node[p]) {
         dbg(1, "name_attached_inst_to_net(): inst %s, pin %d <-- %s\n", 
-              inst[n].instname, p, wire[k].node);
+              inst[n].instname, p, wire[k].node ? wire[k].node : "NULL");
         set_inst_node(n, p, wire[k].node);
         err |= instcheck(n, p);
       } else {
@@ -807,6 +817,18 @@ static int name_attached_inst(int i, double x0, double y0, int sqx, int sqy, con
   return err;
 }
 
+int skip_instance(int i, int lvs_ignore, int mask)
+{
+  int skip = 0;
+  if(xctx->inst[i].ptr < 0) skip = 1;
+  else if(xctx->inst[i].flags & mask) skip = 1;
+  else if(xctx->sym[xctx->inst[i].ptr].flags & mask) skip = 1;
+  else if(lvs_ignore && (xctx->inst[i].flags & LVS_IGNORE)) skip = 1;
+  else if(lvs_ignore && (xctx->sym[xctx->inst[i].ptr].flags & LVS_IGNORE)) skip = 1;
+  return skip;
+}
+
+
 /* what: 
  * Determine if given "ninst" instance has pass-through pins 
  * 0: initialize
@@ -865,7 +887,11 @@ static int instcheck(int n, int p)
   int rects = xctx->sym[inst[n].ptr].rects[PINLAYER];
   int bus_tap = !strcmp(xctx->sym[inst[n].ptr].type, "bus_tap");
   int k = inst[n].ptr;
+  int lvs_ignore=tclgetboolvar("lvs_ignore");
+  int shorted_inst = 
+       (k >=0) && lvs_ignore && ((inst[n].flags & LVS_IGNORE_SHORT) || (sym[k].flags & LVS_IGNORE_SHORT));
 
+  if(!inst[n].node) return 0;
 
   if( xctx->netlist_type == CAD_VERILOG_NETLIST &&
        ((inst[n].flags & VERILOG_IGNORE_INST) || 
@@ -883,15 +909,13 @@ static int instcheck(int n, int p)
        ((inst[n].flags & TEDAX_IGNORE_INST) || 
        (k >= 0 && (sym[k].flags & TEDAX_IGNORE_INST))) ) return 0;
 
+  if( netlist_lvs_ignore &&
+       ((inst[n].flags & LVS_IGNORE_OPEN) || 
+       (k >= 0 && (sym[k].flags & LVS_IGNORE_OPEN))) ) return 0;
 
-
-
-  /* process bus taps : type = bus_tap */
-  if(bus_tap && p == 0) {
-    /* do nothing */
-    dbg(0, "instcheck(): bus tap pin 0: node=%s\n", inst[n].node[p] ? inst[n].node[p] : "NULL");
-  }
-  else if(bus_tap && p == 1) {
+  /* process bus taps : type = bus_tap 
+   * node 1 connects to bus (DATA[15:0]) , node 0 is the tap ([2:0]) */
+  if(rects > 1 && bus_tap && p == 1) {
     char *node_base_name = NULL;
     const char *tap;
     dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[p]);
@@ -933,7 +957,7 @@ static int instcheck(int n, int p)
 
 
   /* should process only symbols with pass-through pins */
-  else if(find_pass_through_symbols(1, n)) {
+  else if(shorted_inst || find_pass_through_symbols(1, n)) {
     int k = inst[n].ptr;
     char *pin_name = NULL;
     my_strdup(_ALLOC_ID_, &pin_name, get_tok_value(xctx->sym[k].rect[PINLAYER][p].prop_ptr, "name", 0));
@@ -941,7 +965,11 @@ static int instcheck(int n, int p)
     for(j = 0; j < rects; ++j) {
       const char *other_pin;
       if(j == p) continue;
-      other_pin = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0);
+      if(shorted_inst) {
+        other_pin = get_tok_value(xctx->sym[k].rect[PINLAYER][p].prop_ptr, "name", 0);
+      } else {
+        other_pin = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0);
+      }
       if(!strcmp(other_pin, pin_name)) {
         dbg(1, "instcheck: inst %s pin %s(%d) <--> pin %s(%d)\n", inst[n].instname, pin_name, p, other_pin, j);
         dbg(1, "instcheck: node: %s\n", inst[n].node[p]);
@@ -1027,6 +1055,7 @@ static int name_nodes_of_pins_labels_and_propagate()
         if( xctx->netlist_type == CAD_SPICE_NETLIST && (inst[i].flags & SPICE_IGNORE_INST)) continue;
         if( xctx->netlist_type == CAD_VHDL_NETLIST && (inst[i].flags & VHDL_IGNORE_INST)) continue;
         if( xctx->netlist_type == CAD_TEDAX_NETLIST && (inst[i].flags & TEDAX_IGNORE_INST)) continue;
+        if( netlist_lvs_ignore && (inst[i].flags & LVS_IGNORE_OPEN)) continue;
       }
       port=0;
       my_strdup2(_ALLOC_ID_, &dir, "");
@@ -1126,7 +1155,7 @@ static int set_unnamed_inst(int i, int j)
   set_inst_node(i, j, tmp_str);
   get_inst_pin_coord(i, j, &x0, &y0);
   get_square(x0, y0, &sqx, &sqy);
-  err |= name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[j]);
+  if(inst[i].node && inst[i].node[j]) err |= name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[j]);
   return err;
 }
 
@@ -1142,6 +1171,7 @@ static int name_unlabeled_instances()
   dbg(2, "name_unlabeled_instances(): naming nets that dont touch labels\n");
   for (i = 0; i < instances; ++i)
   {
+    if(!inst[i].node) continue;
     if(inst[i].ptr != -1) {
       rects=(inst[i].ptr+ xctx->sym)->rects[PINLAYER];
       for(j = 0; j < rects; ++j) {
@@ -1187,9 +1217,12 @@ int prepare_netlist_structs(int for_netl)
 {
   int err = 0;
   char nn[PATH_MAX+30];
+  netlist_lvs_ignore=tclgetboolvar("lvs_ignore");
   for_netlist = for_netl;
   if(for_netlist>0 && xctx->prep_net_structs) return 0;
   else if(!for_netlist && xctx->prep_hi_structs) return 0;
+  
+  dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]);
   reset_flags();
   set_modify(-2); /* to reset floater cached values */
   /* delete instance pins spatial hash, wires spatial hash, node_hash, wires and inst nodes.*/
@@ -1197,7 +1230,6 @@ int prepare_netlist_structs(int for_netl)
     my_snprintf(nn, S(nn), "-----------%s", xctx->sch[xctx->currsch]);
     statusmsg(nn,2);
   }
-  dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]);
   delete_netlist_structs();
   free_simdata(); /* invalidate simulation cache */
   err |= reset_node_data_and_rehash();
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index 8aad665e..627147a5 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -156,6 +156,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
   int i, flag = 0;
   char *type=NULL;
   int top_sub;
+  int lvs_ignore = tclgetboolvar("lvs_ignore");
 
   top_sub = tclgetboolvar("lvs_netlist");
   if(!spice_stop) {
@@ -165,9 +166,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
     err |= traverse_node_hash();  /* print all warnings about unconnected floatings etc */
     for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
     {
-     if(xctx->inst[i].ptr<0) continue;
-     if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+     if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
      if( type && IS_PIN(type) ) {
        if(top_sub && !flag) {
@@ -188,9 +187,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
     if(top_sub) fprintf(fd, "\n");
     for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
     {
-     if(xctx->inst[i].ptr<0) continue;
-     if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+     if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
  
      if( type && !IS_LABEL_OR_PIN(type) ) {
@@ -244,6 +241,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  int split_f;
  Str_hashtable subckt_table = {NULL, 0};
  Str_hashentry *model_entry;
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
 
  split_f = tclgetboolvar("split_files");
  dbg(1, "global_spice_netlist(): invoking push_undo()\n");
@@ -280,9 +278,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  first = 0;
  for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=header' property */
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
   if( type && !strcmp(type,"netlist_commands") ) {
@@ -311,9 +307,7 @@ int global_spice_netlist(int global)  /* netlister driver */
 
  /* print top subckt ipin/opins */
  for(i=0;i<xctx->instances; ++i) {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   dbg(1, "global_spice_netlist(): |%s|\n", type);
   /* 
@@ -335,9 +329,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
                                    and no place=header */
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
   if( type && !strcmp(type,"netlist_commands") ) {
@@ -409,6 +401,7 @@ int global_spice_netlist(int global)  /* netlister driver */
    for(i=0;i<xctx->symbols; ++i)
    {
     if(xctx->sym[i].flags & SPICE_IGNORE_INST) continue;
+    if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
     if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@@ -470,9 +463,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  if(!split_f) {
    for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=end' property */
    {
-    if(xctx->inst[i].ptr<0) continue;
-    if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
-    if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
+    if(skip_instance(i, lvs_ignore, SPICE_IGNORE_INST)) continue;
     my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
     my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
     if( type && !strcmp(type,"netlist_commands") ) {
diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c
index 2f111592..74d238e0 100644
--- a/src/tedax_netlist.c
+++ b/src/tedax_netlist.c
@@ -26,6 +26,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
   int err = 0;
   int i;
   char *type=NULL;
+  int lvs_ignore = tclgetboolvar("lvs_ignore");
 
   if(!tedax_stop) {
     xctx->prep_net_structs = 0;
@@ -35,9 +36,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
   if(!tedax_stop) {
     for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
     {
-     if(xctx->inst[i].ptr<0) continue;
-     if(xctx->inst[i].flags & TEDAX_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[i].ptr].flags & TEDAX_IGNORE_INST) continue;
+     if(skip_instance(i, lvs_ignore, TEDAX_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
      if( type && IS_PIN(type) ) {
        print_tedax_element(fd, i) ;  /* this is the element line  */
@@ -45,9 +44,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
     }
     for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
     {
-     if(xctx->inst[i].ptr<0) continue;
-     if(xctx->inst[i].flags & TEDAX_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[i].ptr].flags & TEDAX_IGNORE_INST) continue;
+     if(skip_instance(i, lvs_ignore, TEDAX_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
 
      if( type && !IS_LABEL_OR_PIN(type) ) {
@@ -131,6 +128,7 @@ int global_tedax_netlist(int global)  /* netlister driver */
  char *subckt_name;
  char *abs_path = NULL;
  Str_hashtable subckt_table = {NULL, 0};
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
 
  xctx->push_undo();
  statusmsg("",2);  /* clear infowindow */
@@ -207,6 +205,7 @@ int global_tedax_netlist(int global)  /* netlister driver */
    for(i=0;i<xctx->symbols; ++i)
    {
     if(xctx->sym[i].flags & TEDAX_IGNORE_INST) continue;
+    if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
     if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
diff --git a/src/token.c b/src/token.c
index 7302a360..778d60e2 100644
--- a/src/token.c
+++ b/src/token.c
@@ -1402,6 +1402,7 @@ void print_vhdl_element(FILE *fd, int inst)
      /* print generic map */
      for(i=0;i<no_of_generics; ++i)
      {
+       if(!xctx->inst[inst].node || !xctx->inst[inst].node[no_of_pins+i]) continue;
        my_strdup(_ALLOC_ID_, &generic_type,get_tok_value(
          (xctx->inst[inst].ptr + xctx->sym)->rect[GENERICLAYER][i].prop_ptr,"type",0));
        my_strdup(_ALLOC_ID_, &generic_value,   xctx->inst[inst].node[no_of_pins+i] );
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index 1e43350a..12770188 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -27,6 +27,8 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
  int err = 0;
  int i;
  char *type=NULL;
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
+
 
  if(!verilog_stop) {
    xctx->prep_net_structs = 0;
@@ -43,9 +45,7 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
  {
    for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
    {
-    if(xctx->inst[i].ptr<0) continue;
-    if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-    if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+    if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
     dbg(2, "verilog_netlist():       into the netlisting loop\n");
     my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
     if( type &&
@@ -95,6 +95,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  int split_f;
  const char *fmt_attr = NULL;
  Str_hashtable subckt_table = {NULL, 0};
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
 
  split_f = tclgetboolvar("split_files");
  xctx->push_undo();
@@ -128,9 +129,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  fmt_attr = xctx->format ? xctx->format : "verilog_format";
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
   {
@@ -160,9 +159,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  tmp=0;
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"opin"))==0)
   {
@@ -176,9 +173,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"iopin"))==0)
   {
@@ -192,11 +187,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  dbg(1, "global_verilog_netlist(): printing top level input pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
-  if(xctx->inst[i].ptr<0) continue;
-  if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
-    continue;
-  }
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"ipin"))==0)
   {
@@ -224,9 +215,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  dbg(1, "global_verilog_netlist(): printing top level out pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"opin"))==0)
   {
@@ -245,9 +234,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"iopin"))==0)
   {
@@ -266,9 +253,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  dbg(1, "global_verilog_netlist(): printing top level input pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"ipin"))==0)
   {
@@ -290,9 +275,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  fprintf(fd,"---- begin user architecture code\n");
 
  for(i=0;i<xctx->instances; ++i) {
-   if(xctx->inst[i].ptr<0) continue;
-   if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
-   if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
+   if(skip_instance(i, lvs_ignore, VERILOG_IGNORE_INST)) continue;
    my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
    if(type && !strcmp(type,"netlist_commands")) {
      fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@@ -347,6 +330,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
    for(i=0;i<xctx->symbols; ++i)
    {
     if(xctx->sym[i].flags & VERILOG_IGNORE_INST) continue;
+    if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
     if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path)) {
@@ -438,6 +422,7 @@ int verilog_block_netlist(FILE *fd, int i)
   const char *sym_def;
   char *extra_ptr, *saveptr1, *extra_token, *extra = NULL, *extra2=NULL;
   char *name = NULL;
+  int lvs_ignore = tclgetboolvar("lvs_ignore");
 
   my_strdup(_ALLOC_ID_, &name, tcl_hook2(xctx->sym[i].name));
   split_f = tclgetboolvar("split_files");
@@ -474,9 +459,7 @@ int verilog_block_netlist(FILE *fd, int i)
     fmt_attr = xctx->format ? xctx->format : "verilog_format";
     for(j=0;j<xctx->instances; ++j)
     {
-     if(xctx->inst[j].ptr<0) continue;
-     if(xctx->inst[j].flags & VERILOG_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[j].ptr].flags & VERILOG_IGNORE_INST) continue;
+     if(skip_instance(j, lvs_ignore, VERILOG_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
      if( type && ( strcmp(type,"timescale")==0  || strcmp(type,"verilog_preprocessor")==0) )
      {
@@ -576,9 +559,7 @@ int verilog_block_netlist(FILE *fd, int i)
     err |= verilog_netlist(fd, verilog_stop);
     fprintf(fd,"---- begin user architecture code\n");
     for(l=0;l<xctx->instances; ++l) {
-      if(xctx->inst[l].ptr<0) continue;
-      if(xctx->inst[l].flags & VERILOG_IGNORE_INST) continue;
-      if(xctx->sym[xctx->inst[l].ptr].flags & VERILOG_IGNORE_INST) continue;
+      if(skip_instance(l, lvs_ignore, VERILOG_IGNORE_INST)) continue;
       if(xctx->netlist_count &&
         !strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
   
diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c
index 00226841..852d8cae 100644
--- a/src/vhdl_netlist.c
+++ b/src/vhdl_netlist.c
@@ -27,6 +27,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
  int err = 0;
  int i,l;
  char *type=NULL;
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
 
  if(!vhdl_stop) {
    xctx->prep_net_structs = 0;
@@ -38,10 +39,9 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
  fprintf(fd, "//// begin user declarations\n");
  for(l=0;l<xctx->instances; ++l)
  {
-  if(xctx->inst[l].ptr<0) continue;
+  if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
   if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
-  if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
+
   if(!strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "arch_declarations") )
    fprintf(fd, "%s\n", xctx->inst[l].prop_ptr?  xctx->inst[l].prop_ptr: "");
  }
@@ -55,9 +55,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
  fprintf(fd, "//// begin user attributes\n");
  for(l=0;l<xctx->instances; ++l)
  {
-  if(xctx->inst[l].ptr<0) continue;
-  if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
+  if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
   if( type && (strcmp(type,"attributes"))==0)
   {
@@ -72,9 +70,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
  {
    for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
    {                       /* dont print elements with vhdl_ignore=true set in symbol */
-    if(xctx->inst[i].ptr<0) continue;
-    if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-    if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+    if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
     dbg(2, "vhdl_netlist():       into the netlisting loop\n");
     my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
     if( type &&
@@ -124,6 +120,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  char *abs_path = NULL;
  int split_f;
  Str_hashtable subckt_table = {NULL, 0};
+ int lvs_ignore = tclgetboolvar("lvs_ignore");
 
  split_f = tclgetboolvar("split_files");
  xctx->push_undo();
@@ -155,9 +152,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  dbg(1, "global_vhdl_netlist(): printing top level packages\n");
   for(i=0;i<xctx->instances; ++i)
   {
-   if(xctx->inst[i].ptr<0) continue;
-   if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-   if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+   if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
    my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
    if( type && (strcmp(type,"package"))==0)
    {
@@ -172,9 +167,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  dbg(1, "global_vhdl_netlist(): printing top level use statements\n");
   for(i=0;i<xctx->instances; ++i)
   {
-   if(xctx->inst[i].ptr<0) continue;
-   if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-   if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+   if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
    my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
    if( type && (strcmp(type,"use"))==0)
    {
@@ -239,9 +232,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  tmp=0;
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
   if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@@ -258,9 +249,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  dbg(1, "global_vhdl_netlist(): printing top level inout pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
   if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@@ -277,9 +266,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  dbg(1, "global_vhdl_netlist(): printing top level input pins\n");
  for(i=0;i<xctx->instances; ++i)
  {
-  if(xctx->inst[i].ptr<0) continue;
-  if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-  if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+  if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
   my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
   if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
   my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@@ -297,9 +284,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  dbg(1, "global_vhdl_netlist(): printing top level port attributes\n");
   for(i=0;i<xctx->instances; ++i)
   {
-   if(xctx->inst[i].ptr<0) continue;
-   if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-   if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+   if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
    my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
    if( type && (strcmp(type,"port_attributes"))==0)
    {
@@ -320,6 +305,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  {
   if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
   if(xctx->sym[j].flags & VHDL_IGNORE_INST) continue;
+  if(lvs_ignore && (xctx->sym[j].flags & LVS_IGNORE)) continue;
   if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
      strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
   my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[j].name), ""));
@@ -377,9 +363,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
  fprintf(fd,"//// begin user architecture code\n");
 
  for(i=0;i<xctx->instances; ++i) {
-   if(xctx->inst[i].ptr<0) continue;
-   if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
-   if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
+   if(skip_instance(i, lvs_ignore, VHDL_IGNORE_INST)) continue;
    my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
    if(type && !strcmp(type,"netlist_commands")) {
      fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@@ -434,6 +418,7 @@ int global_vhdl_netlist(int global)  /* netlister driver */
    for(i=0;i<xctx->symbols; ++i)
    {
     if(xctx->sym[i].flags & VHDL_IGNORE_INST) continue;
+    if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
     if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@@ -521,6 +506,7 @@ int vhdl_block_netlist(FILE *fd, int i)
   const char *str_tmp;
   int split_f;
   const char *sym_def;
+  int lvs_ignore = tclgetboolvar("lvs_ignore");
 
   split_f = tclgetboolvar("split_files");
   if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"vhdl_stop",0),"true") )
@@ -553,10 +539,8 @@ int vhdl_block_netlist(FILE *fd, int i)
     dbg(1, "vhdl_block_netlist():       packages\n");
     for(l=0;l<xctx->instances; ++l)
     {
-     if(xctx->inst[l].ptr<0) continue;
+     if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
      if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
-     if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
      if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
       fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
     }
@@ -564,10 +548,8 @@ int vhdl_block_netlist(FILE *fd, int i)
     dbg(1, "vhdl_block_netlist():       use statements\n");
     for(l=0;l<xctx->instances; ++l)
     {
-     if(xctx->inst[l].ptr<0) continue;
+     if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
      if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
-     if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
      if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
       fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
     }
@@ -608,9 +590,7 @@ int vhdl_block_netlist(FILE *fd, int i)
     dbg(1, "vhdl_block_netlist():       port attributes\n");
     for(l=0;l<xctx->instances; ++l)
     {
-     if(xctx->inst[l].ptr<0) continue;
-     if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-     if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
+     if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
      my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
      if( type && (strcmp(type,"port_attributes"))==0)
      {
@@ -645,9 +625,7 @@ int vhdl_block_netlist(FILE *fd, int i)
           found=0;
           for(l=0;l<xctx->instances; ++l)
           {
-            if(xctx->inst[l].ptr<0) continue;
-            if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-            if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
+            if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
             if(!xctx->x_strcmp(xctx->sym[j].name, tcl_hook2(xctx->inst[l].name)))
             {
               found=1; break;
@@ -693,9 +671,7 @@ int vhdl_block_netlist(FILE *fd, int i)
     fprintf(fd,"//// begin user architecture code\n");
   
     for(l=0;l<xctx->instances; ++l) {
-      if(xctx->inst[l].ptr<0) continue;
-      if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
-      if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
+      if(skip_instance(l, lvs_ignore, VHDL_IGNORE_INST)) continue;
       if(xctx->netlist_count &&
         !strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
   
diff --git a/src/xschem.h b/src/xschem.h
index afeeeddf..3918112a 100644
--- a/src/xschem.h
+++ b/src/xschem.h
@@ -177,6 +177,9 @@ extern char win_temp_dir[PATH_MAX];
 #define TEDAX_IGNORE_INST 128
 #define IGNORE_INST 256
 #define HIDE_SYMBOL_TEXTS 512
+#define LVS_IGNORE_SHORT 1024 /* flag set if inst/symbol has lvs_ignore=short */
+#define LVS_IGNORE_OPEN 2048  /* flag set if inst/symbol has lvs_ignore=open */
+#define LVS_IGNORE (LVS_IGNORE_SHORT | LVS_IGNORE_OPEN)
 #define CADMAXGRIDPOINTS 512
 #define CADMAXHIER 40
 #define CADCHUNKALLOC 512 /*  was 256  20102004 */
@@ -551,6 +554,8 @@ typedef struct
                 * bit 8: IGNORE_INST, instance must be ignored based on *_ignore=true and netlisting mode.
                 *        used in draw.c
                 * bit 9: HIDE_SYMBOL_TEXTS, hide_texts=true on instance (not used in symbol, but keep free)
+                * bit 10: LVS_IGNORE_SHORT: short together all nets connected to symbol if lvs_ignore tcl var set
+                * bit 11: LVS_IGNORE_OPEN: remove symbol leaving all connected nets open if lvs_ignore tcl var set
                 */
 
 } xSymbol;
@@ -587,6 +592,8 @@ typedef struct
 	        * bit 8: IGNORE_INST, instance must be ignored based on *_ignore=true and netlisting mode.
                 *        used in draw.c
 	        * bit 9: HIDE_SYMBOL_TEXTS, hide_texts=true (hide_texts=true attribute on instance)
+                * bit 10: LVS_IGNORE_SHORT: short together all nets connected to symbol if lvs_ignore tcl var set
+                * bit 11: LVS_IGNORE_OPEN: remove symbol leaving all connected nets open if lvs_ignore tcl var set
                 */
   char *prop_ptr;
   char **node;
@@ -1522,6 +1529,7 @@ extern void display_hilights(int what, char **str);
 extern void redraw_hilights(int clear);
 extern void set_tcl_netlist_type(void);
 extern int prepare_netlist_structs(int for_netlist);
+extern int skip_instance(int i, int lvs_ignore, int mask);
 extern int compare_schematics(const char *filename);
 extern int warning_overlapped_symbols(int sel);
 extern void free_simdata(void);
diff --git a/src/xschem.tcl b/src/xschem.tcl
index b8daaf39..63eea340 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -6197,6 +6197,8 @@ tclcommand=\"xschem raw_read \$netlist_dir/[file tail [file rootname [xschem get
       xschem set format {}
     }
   }
+  $topwin.menubar.simulation.menu add checkbutton -label "Set 'lvs_ignore' variable" \
+         -variable lvs_ignore -command {xschem rebuild_connectivity; xschem unhilight_all}
   $topwin.menubar.simulation.menu add command -label {Changelog from current hierarchy} -command {
     viewdata [list_hierarchy]
   }
@@ -6503,6 +6505,7 @@ set_ne netlist_type spice
 set_ne local_netlist_dir 0 ;# if set use <sch_dir>/simulation for netlist and sims
 set_ne bus_replacement_char {} ;# use {<>} to replace [] with <> in bussed signals
 set_ne lvs_netlist 0
+set_ne lvs_ignore 0
 set_ne hide_empty_graphs 0 ;# if set to 1 waveform boxes will be hidden if no raw file loaded
 set_ne spiceprefix 1
 set_ne verilog_2001 1
diff --git a/xschem_library/devices/short.sym b/xschem_library/devices/short.sym
index b0500c84..4b127611 100644
--- a/xschem_library/devices/short.sym
+++ b/xschem_library/devices/short.sym
@@ -3,7 +3,7 @@ v {xschem version=3.4.0 file_version=1.2
 G {}
 K {type=show_label
 template="name=x1 value=0.1"
-format="@name @pinlist @symname value=@value"
+format="* short @name : @#0:net_name <--> @#1:net_name"
 highlight=true}
 V {}
 S {}
diff --git a/xschem_library/examples/0_examples_top.sch b/xschem_library/examples/0_examples_top.sch
index d00281d6..ebd387c5 100644
--- a/xschem_library/examples/0_examples_top.sch
+++ b/xschem_library/examples/0_examples_top.sch
@@ -45,12 +45,12 @@ A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511
 P 1 10 880 -490 870 -550 950 -530 910 -510 940 -480 920 -480 910 -460 890 -500 880 -480 880 -490 {dash=3}
 P 4 6 830 -470 830 -560 820 -510 820 -550 810 -520 810 -490 {}
 P 15 11 870 -520 880 -560 900 -530 910 -550 920 -520 940 -530 920 -490 890 -500 860 -480 840 -530 870 -520 {fill=true}
-T {Welcome to XSCHEM!} 110 -1100 0 0 1 1 {layer=5}
+T {Welcome to XSCHEM!} 110 -1130 0 0 1 1 {layer=5}
 T {This is a test schematic window 
 
 On the left you see some sample circuits. You may descend into any of these by selecting one with a left mouse button click and
 pressing the 'e' key, or by menu 'Edit -> Push Schematic'. You can return here after descending into a schematic by hitting 
-'<Ctrl>-e' or by menu 'Edit -> Pop'.} 60 -1030 0 0 0.4 0.4 {}
+'<Ctrl>-e' or by menu 'Edit -> Pop'.} 60 -1060 0 0 0.4 0.4 {}
 T {Lines} 960 -680 0 0 0.6 0.6 {layer=4}
 T {Rectangles} 960 -620 0 0 0.6 0.6 {layer=4}
 T {Polygons} 960 -530 0 0 0.6 0.6 {layer=4}
@@ -87,16 +87,16 @@ N 380 -310 640 -310 {lab=BUS[4:0]}
 N 510 -400 510 -320 {lab=BUS[1]}
 N 410 -350 410 -320 {lab=BUS[2]}
 N 460 -400 460 -320 {lab=BUS[2:1]}
-C {poweramp.sym} 480 -790 0 0 {name=x1
+C {poweramp.sym} 480 -820 0 0 {name=x1
 tclcommand="xschem descend"}
-C {tesla.sym} 160 -670 0 0 {name=x2}
-C {test_ne555.sym} 160 -630 0 0 {name=x3}
-C {test_lm324.sym} 160 -590 0 0 {name=x4}
-C {osc.sym} 160 -710 0 0 {name=x5}
+C {tesla.sym} 160 -700 0 0 {name=x2}
+C {test_ne555.sym} 160 -660 0 0 {name=x3}
+C {test_lm324.sym} 160 -620 0 0 {name=x4}
+C {osc.sym} 160 -740 0 0 {name=x5}
 C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
-C {cmos_example.sym} 160 -750 0 0 {name=x6}
-C {greycnt.sym} 160 -790 0 0 {name=x8}
-C {loading.sym} 160 -830 0 0 {name=x9}
+C {cmos_example.sym} 160 -780 0 0 {name=x6}
+C {greycnt.sym} 160 -820 0 0 {name=x8}
+C {loading.sym} 160 -860 0 0 {name=x9}
 C {inv_bsource.sym} 880 -320 0 0 {name=B1 TABLE="1.4 3.0 1.6 0.0"}
 C {launcher.sym} 460 -140 0 0 {name=h1 
 descr="XSCHEM ON REPO.HU" 
@@ -113,17 +113,17 @@ url="$\{XSCHEM_SHAREDIR\}/../doc/xschem/index.html"
 program=x-www-browser
 
 }
-C {rlc.sym} 160 -870 0 0 {name=x0}
+C {rlc.sym} 160 -900 0 0 {name=x0}
 C {lab_pin.sym} 640 -310 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
 C {bus_connect.sym} 500 -310 0 0 {name=l3 lab=BUS[1]}
 C {bus_connect_nolab.sym} 400 -310 0 0 {name=r1}
 C {lab_pin.sym} 410 -350 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
-C {LCC_instances.sym} 160 -550 0 0 {name=x7}
-C {test_backannotated_subckt.sym} 160 -510 0 0 {name=x10}
-C {plot_manipulation.sym} 160 -470 0 0 {name=x11}
-C {logic_test.sym} 160 -430 0 0 {name=x12}
-C {simulate_ff.sym} 160 -390 0 0 {name=x13}
-C {test_mos_verilog.sym} 160 -350 0 0 {name=x14}
+C {LCC_instances.sym} 160 -580 0 0 {name=x7}
+C {test_backannotated_subckt.sym} 160 -540 0 0 {name=x10}
+C {plot_manipulation.sym} 160 -500 0 0 {name=x11}
+C {logic_test.sym} 160 -460 0 0 {name=x12}
+C {simulate_ff.sym} 160 -420 0 0 {name=x13}
+C {test_mos_verilog.sym} 160 -380 0 0 {name=x14}
 C {launcher.sym} 1265 -225 0 0 {name=h5 
 descr=" Ctrl-Left-Click to load/
 unload waveforms" 
@@ -1456,19 +1456,20 @@ xwtAgA9ve8fHC0Dod8blIpQLQJBdgRgxavQ/AAAAgEslwD6d7SiMdxwqP41maeirFRxABH/Rb+tVM0DO
 cwtAyKwqggMC8z8AAABAXz/APixDHOviNio/cIyWTt0GHEAHmaX3NW0zQHJvU5F/bTNA3V5CW3kqoL85tJeeXUIJQIB/waNeQglAcFfF8JIdC0DY7tjwBPjxPwAAALCc
 UsA+"
 }
-C {test_ac.sym} 160 -310 0 0 {name=x15}
-C {rom8k.sym} 480 -830 0 0 {name=x17}
-C {test_doublepin.sym} 160 -270 0 0 {name=x19}
-C {classD_amp.sym} 480 -870 0 0 {name=x20}
-C {delta_sigma.sym} 480 -710 0 0 {name=x21}
-C {solar_panel.sym} 480 -670 0 0 {name=xsolar}
-C {test_extracted_netlist.sym} 160 -230 0 0 {name=x23
+C {test_ac.sym} 160 -340 0 0 {name=x15}
+C {rom8k.sym} 480 -860 0 0 {name=x17}
+C {test_doublepin.sym} 160 -300 0 0 {name=x19}
+C {classD_amp.sym} 480 -900 0 0 {name=x20}
+C {delta_sigma.sym} 480 -740 0 0 {name=x21}
+C {solar_panel.sym} 480 -700 0 0 {name=xsolar}
+C {test_extracted_netlist.sym} 160 -260 0 0 {name=x23
 tclcommand="xschem descend"}
-C {poweramp_lcc.sym} 480 -750 0 0 {name=x16
+C {poweramp_lcc.sym} 480 -780 0 0 {name=x16
 tclcommand="xschem descend"}
-C {test_symbolgen.sym} 480 -630 0 0 {name=x18}
-C {inst_sch_select.sym} 480 -590 0 0 {name=x24}
-C {test_bus_tap.sym} 480 -550 0 0 {name=x22}
+C {test_symbolgen.sym} 480 -660 0 0 {name=x18}
+C {inst_sch_select.sym} 480 -620 0 0 {name=x24}
+C {test_bus_tap.sym} 480 -580 0 0 {name=x22}
 C {bus_tap.sym} 450 -310 1 1 {name=l5 lab=[2:1]}
-C {test_jfet.sym} 480 -510 0 0 {name=x25}
-C {test_short_option.sym} 480 -470 0 0 {name=x26}
+C {test_jfet.sym} 480 -540 0 0 {name=x25}
+C {test_short_option.sym} 480 -500 0 0 {name=x26}
+C {test_lvs_ignore.sym} 480 -460 0 0 {name=x27}
diff --git a/xschem_library/examples/test_lvs_ignore.sch b/xschem_library/examples/test_lvs_ignore.sch
new file mode 100644
index 00000000..1529f5c0
--- /dev/null
+++ b/xschem_library/examples/test_lvs_ignore.sch
@@ -0,0 +1,102 @@
+v {xschem version=3.4.0 file_version=1.2
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+L 7 980 -150 1160 -150 {}
+P 4 7 210 -290 210 -370 220 -370 210 -390 200 -370 210 -370 210 -290 {}
+T {Title symbol has embedded TCL command
+to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7}
+T {Set tcl variable lvs_ignore to:
+- 1 to short elements with lvs_ignore=short attribute set
+    to disable elements with lvs_ignore=open attribute set
+- 0 for normal netlisting} 60 -1030 0 0 1 1 {}
+T {tcleval(lvs_ignore=$lvs_ignore)} 980 -190 0 0 0.6 0.6 {name=l1}
+T {This component has attribute
+lvs_ignore=open} 910 -370 0 0 0.4 0.4 {}
+T {This component has attribute
+lvs_ignore=short} 170 -560 0 0 0.4 0.4 {}
+T {This is the lab_show component
+it is used only to display the net
+name it is attached to. This works if
+Options->Show net names on symbol pins
+is enabled.} 220 -350 0 0 0.4 0.4 {}
+N 850 -430 920 -430 {
+lab=#net1}
+N 850 -430 850 -380 {
+lab=#net1}
+N 130 -540 130 -530 {
+lab=VDD}
+N 130 -470 130 -430 {
+lab=#net2}
+N 130 -430 280 -430 {
+lab=#net2}
+N 360 -430 430 -430 {
+lab=STARTUP}
+N 130 -430 130 -380 {
+lab=#net2}
+N 130 -320 130 -290 {
+lab=GND}
+N 850 -580 850 -570 {
+lab=VDD}
+N 850 -510 850 -430 {
+lab=#net1}
+N 920 -430 1010 -430 {
+lab=#net1}
+N 1090 -430 1110 -430 {
+lab=#net3}
+N 850 -320 850 -290 {
+lab=GND}
+C {title.sym} 160 -30 0 0 {name=l1
+author="tcleval([
+  if \{$show_pin_net_names == 0\} \{
+    set lvs_ignore 0
+    set show_pin_net_names 1
+    xschem update_all_sym_bboxes
+  \}
+  return \{Stefan Schippers\}
+])"
+}
+C {launcher.sym} 750 -90 0 0 {name=h1
+descr="Toggle lvs_ignore variable and
+rebuild connectivity"
+tclcommand="
+if \{![info exists lvs_ignore]\} \{
+   set lvs_ignore 1
+\} else \{
+  set lvs_ignore [expr \{!$lvs_ignore\}]
+\}
+xschem rebuild_connectivity
+xschem unhilight_all
+"}
+C {vsource.sym} 850 -350 0 0 {name=V2 value=0
+lvs_ignore=open}
+C {inv_ngspice.sym} 1050 -430 0 0 {name=x5 ROUT=1000}
+C {lab_show.sym} 920 -430 0 1 {name=l10 }
+C {lab_show.sym} 1110 -430 0 1 {name=l3 }
+C {gnd.sym} 850 -290 0 0 {name=l4 lab=GND}
+C {res.sym} 130 -500 0 0 {name=R1
+value=100MEG
+footprint=1206
+device=resistor
+m=1
+lvs_ignore=short}
+C {vdd.sym} 130 -540 0 0 {name=l12 lab=VDD}
+C {capa.sym} 130 -350 0 0 {name=C1
+m=1
+value=1p
+footprint=1206
+device="ceramic capacitor"}
+C {gnd.sym} 130 -290 0 0 {name=l13 lab=GND}
+C {lab_show.sym} 170 -430 2 0 {name=l14 }
+C {lab_pin.sym} 430 -430 0 1 {name=p1 sig_type=std_logic lab=STARTUP}
+C {inv_ngspice.sym} 320 -430 0 0 {name=x2 ROUT=1000}
+C {res.sym} 850 -540 0 0 {name=R2
+value=100MEG
+footprint=1206
+device=resistor
+m=1
+}
+C {vdd.sym} 850 -580 0 0 {name=l6 lab=VDD}
diff --git a/xschem_library/examples/test_lvs_ignore.sym b/xschem_library/examples/test_lvs_ignore.sym
new file mode 100644
index 00000000..8b60ba0f
--- /dev/null
+++ b/xschem_library/examples/test_lvs_ignore.sym
@@ -0,0 +1,11 @@
+v {xschem version=3.4.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -94.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
diff --git a/xschem_library/examples/test_short_option.sch b/xschem_library/examples/test_short_option.sch
index ce460793..aba75e1d 100644
--- a/xschem_library/examples/test_short_option.sch
+++ b/xschem_library/examples/test_short_option.sch
@@ -12,8 +12,7 @@ P 4 7 950 -470 950 -380 940 -380 950 -360 960 -380 950 -380 950 -470 {}
 T {Title symbol has embedded TCL command
 to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7}
 T {Set tcl variable IGNORE to 1 or 0 to
-enable / disable some components in 
-title instance attributes} 50 -940 0 0 1 1 {}
+enable / disable some components} 50 -940 0 0 1 1 {}
 T {tcleval(IGNORE=$IGNORE)} 920 -230 0 0 0.6 0.6 {name=l1}
 T {The short component is a pass-through symbol. It can be used to short two nets.
 Setting spice_ignore=true will disable the component and remove the short.} 80 -690 0 0 0.4 0.4 {}
@@ -25,15 +24,15 @@ is enabled.} 650 -600 0 0 0.4 0.4 {}
 N 120 -230 170 -230 {
 lab=NET_A}
 N 470 -230 520 -230 {
-lab=NET_A}
+lab=#net1}
 N 170 -330 170 -230 {
 lab=NET_A}
 N 470 -330 470 -230 {
-lab=NET_A}
+lab=#net1}
 N 170 -330 290 -330 {
 lab=NET_A}
 N 350 -330 470 -330 {
-lab=NET_A}
+lab=#net1}
 N 120 -420 170 -420 {
 lab=NET_C}
 N 470 -420 520 -420 {
@@ -51,15 +50,15 @@ lab=NET_C}
 N 170 -420 290 -420 {
 lab=NET_C}
 N 370 -230 470 -230 {
-lab=NET_A}
+lab=#net1}
 N 170 -230 290 -230 {
 lab=NET_A}
 N 600 -420 650 -420 {
-lab=#net1}
+lab=#net2}
 N 650 -400 650 -340 {
-lab=#net1}
+lab=#net2}
 N 650 -340 740 -340 {
-lab=#net1}
+lab=#net2}
 N 650 -300 740 -300 {
 lab=NET_B}
 N 650 -300 650 -230 {
@@ -67,17 +66,17 @@ lab=NET_B}
 N 600 -230 650 -230 {
 lab=NET_B}
 N 860 -320 900 -320 {
-lab=#net1}
+lab=#net2}
 N 650 -400 750 -400 {
-lab=#net1}
+lab=#net2}
 N 810 -400 860 -400 {
-lab=#net1}
+lab=#net2}
 N 860 -400 860 -320 {
-lab=#net1}
+lab=#net2}
 N 650 -420 650 -400 {
-lab=#net1}
+lab=#net2}
 N 840 -320 860 -320 {
-lab=#net1}
+lab=#net2}
 C {lab_pin.sym} 120 -230 0 0 {name=p3 sig_type=std_logic lab=NET_A}
 C {iopin.sym} 80 -140 0 1 { name=p4 lab=NET_A }
 C {title.sym} 160 -30 0 0 {name=l1
@@ -102,15 +101,17 @@ spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{f
 C {lab_show.sym} 470 -520 0 1 {name=l3 }
 C {iopin.sym} 80 -110 0 1 { name=p7 lab=NET_C }
 C {lab_show.sym} 650 -420 0 1 {name=l5 }
-C {iv.sym} 560 -420 0 0 {name=x3 delay="70 ps" del=70}
-C {iv.sym} 560 -230 0 0 {name=x6 delay="70 ps" del=70}
-C {iv.sym} 330 -420 0 0 {name=x7 delay="70 ps" del=70
+C {inv_ngspice.sym} 560 -420 0 0 {name=x3  
+ROUT=1000}
+C {inv_ngspice.sym} 560 -230 0 0 {name=x6  
+ROUT=1000}
+C {inv_ngspice.sym} 330 -420 0 0 {name=x7  
 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
-}
-C {iv.sym} 330 -230 0 0 {name=x8 delay="70 ps" del=70
+ROUT=1000}
+C {inv_ngspice.sym} 330 -230 0 0 {name=x8  
 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
-}
-C {nd2.sym} 780 -320 0 0 {name=a1 del=120
+ROUT=1000}
+C {and_ngspice.sym} 780 -320 0 0 {name=x4 ROUT=1000 
 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
 }
 C {short.sym} 780 -400 0 0 {name=x1