From 3528634124b9778a8160bc596dca134fcac47999 Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Sat, 2 Jan 2021 18:56:42 +0100 Subject: [PATCH] Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe --- doc/xschem_man/commands.html | 14 +- .../tutorial_ngspice_backannotation.html | 2 +- src/callback.c | 6 + src/check.c | 5 +- src/draw.c | 9 +- src/hash_iterator.c | 148 ++++++++---------- src/hilight.c | 120 +++++++++++++- src/keys.help | 6 + src/psprint.c | 3 +- src/scheduler.c | 7 + src/svgdraw.c | 3 +- src/xschem.h | 21 ++- src/xschem.tcl | 2 + xschem_library/devices/ngspice_probe.sym | 4 +- 14 files changed, 245 insertions(+), 105 deletions(-) diff --git a/doc/xschem_man/commands.html b/doc/xschem_man/commands.html index 37ca2f8e..d8a7db8c 100644 --- a/doc/xschem_man/commands.html +++ b/doc/xschem_man/commands.html @@ -85,6 +85,7 @@ LeftButton Double click Terminate Polygon placement ---------------------------------------------------------------------- - BackSpace Back to parent schematic - Delete Delete selected objects +shift Delete select all connected wires/labels/probes - Insert Insert element from library - Down Move down ctrl Enter Confirm closing dialog boxes @@ -101,6 +102,10 @@ ctrl Enter Confirm closing dialog boxes ctrl '#' Rename components with duplicated name (refdes) - '5' View only probes ctrl '0-9' set current layer (4 -13) + '0' set selected net or label to logic value '0' + '1' set selected net or label to logic value '1' + '2' set selected net or label to logic value 'X' + '3' toggle selected net or label: 1->0, 0->1, X->X - 'a' Make symbol from pin list of current schematic ctrl 'a' Select all shift 'A' Toggle show netlist @@ -112,8 +117,8 @@ ctrl 'c' Save to clipboard shift 'C' Start arc placement shift+ctrl 'C' Start circle placement alt 'C' Toggle dim/brite background with rest of layers -ctrl 'e' Back to parent schematic shift 'D' Delete files +ctrl 'e' Back to parent schematic - 'e' Descend to schematic alt 'e' Edit selected schematic in a new window '\' Toggle Full screen @@ -131,22 +136,23 @@ ctrl 'h' Follow http link or execute command (url, tclcommand pro shift 'H' Attach net labels to selected instance - 'i' Descend to symbol alt 'i' Edit selected symbol in a new window -shift 'J' Create symbol from pin list alt+shift 'J' Create labels with 'i' prefix from highlighted nets/pins alt 'j' Create labels without 'i' prefix from highlighted nets/pins ctrl 'j' Create ports from highlight nets alt+ctrl 'j' Print list of highlighted nets/pins with label expansion -- 'j' Print list of highlighted nets/pins shift 'J' create xplot plot file for ngspice in simulation directory (just type xplot in ngspice) +- 'j' Print list of highlighted nets/pins - 'k' Hilight selected nets ctrl+shift 'K' highlight net passing through elements with 'propagate_to' property set on pins shift 'K' Unhilight all nets ctrl 'k' Unhilight selected nets +alt 'k' Select all nets attached to selected wire / label / pin. - 'l' Start line ctrl 'l' Make schematic view from selected symbol -alt 'l' add lab_pin.sym to schematic alt+shift 'l' add lab_wire.sym to schematic +alt 'l' add lab_pin.sym to schematic +ctrl+shift 'o' Load most recent schematic ctrl 'o' Load schematic - 'm' Move selected obj. shift 'N' Hierarchical netlist diff --git a/doc/xschem_man/tutorial_ngspice_backannotation.html b/doc/xschem_man/tutorial_ngspice_backannotation.html index a1699086..04955260 100644 --- a/doc/xschem_man/tutorial_ngspice_backannotation.html +++ b/doc/xschem_man/tutorial_ngspice_backannotation.html @@ -180,7 +180,7 @@ write cmos_example.raw

- The syntax is a bit clompex, considering the verbosity of TCL and the strange ngspice naming syntax, however + The syntax is a bit complex, considering the verbosity of TCL and the strange ngspice naming syntax, however once a working one is created changing the expression is easy.

diff --git a/src/callback.c b/src/callback.c index a858b246..b472c09b 100644 --- a/src/callback.c +++ b/src/callback.c @@ -638,6 +638,12 @@ int callback(int event, int mx, int my, KeySym key, dbg(1, "callback(): new color: %d\n",color_index[xctx->rectcolor]); break; } + /* select connected nets/pins/lanels */ + if(key==XK_Delete && (xctx->ui_state & SELECTION) && state == ShiftMask ) + { + if(xctx->semaphore >= 2) break; + select_connected_wires();break; + } if(key==XK_Delete && (xctx->ui_state & SELECTION) ) /* delete objects */ { if(xctx->semaphore >= 2) break; diff --git a/src/check.c b/src/check.c index 75f735cd..63ef573b 100644 --- a/src/check.c +++ b/src/check.c @@ -51,6 +51,7 @@ void update_conn_cues(int draw_cues, int dr_win) double x1, y1, x2, y2; struct wireentry *wireptr; xWire * const wire = xctx->wire; + struct iterator_ctx ctx; hash_wires(); /* must be done also if wires==0 to clear wiretable */ if(!xctx->wires) return; @@ -60,7 +61,7 @@ void update_conn_cues(int draw_cues, int dr_win) y1 = Y_TO_XSCHEM(xctx->areay1); x2 = X_TO_XSCHEM(xctx->areax2); y2 = Y_TO_XSCHEM(xctx->areay2); - for(init_wire_iterator(x1, y1, x2, y2); ( wireptr = wire_iterator_next() ) ;) { + for(init_wire_iterator(&ctx, x1, y1, x2, y2); ( wireptr = wire_iterator_next(&ctx) ) ;) { k=wireptr->n; /* optimization when editing small areas (detailed zoom) of a huge schematic */ if(LINE_OUTSIDE(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, x1, y1, x2, y2)) continue; @@ -98,7 +99,7 @@ void update_conn_cues(int draw_cues, int dr_win) dbg(3, "update_conn_cues(): check3\n"); if(draw_cues) { save_draw = draw_window; draw_window = dr_win; - for(init_wire_iterator(x1, y1, x2, y2); ( wireptr = wire_iterator_next() ) ;) { + for(init_wire_iterator(&ctx, x1, y1, x2, y2); ( wireptr = wire_iterator_next(&ctx) ) ;) { i = wireptr->n; /* optimization when editing small areas (detailed zoom) of a huge schematic */ if(LINE_OUTSIDE(wire[i].x1, wire[i].y1, diff --git a/src/draw.c b/src/draw.c index ed3d2f7f..4e9f8efc 100644 --- a/src/draw.c +++ b/src/draw.c @@ -1498,6 +1498,7 @@ void draw(void) hash_wires(); } if(!only_probes) { + struct iterator_ctx ctx; dbg(3, "draw(): check4\n"); for(c=0;cpoly[c][i]; drawpolygon(c, NOW, p->x, p->y, p->points, p->fill, p->dash); } - if(use_hash) init_inst_iterator(x1, y1, x2, y2); + if(use_hash) init_inst_iterator(&ctx, x1, y1, x2, y2); else i = -1; while(1) { if(use_hash) { - if( !(instanceptr = inst_iterator_next())) break; + if( !(instanceptr = inst_iterator_next(&ctx))) break; i = instanceptr->n; } else { @@ -1551,11 +1552,11 @@ void draw(void) drawline(c, END, 0.0, 0.0, 0.0, 0.0, 0); } if(draw_single_layer==-1 || draw_single_layer==WIRELAYER) { - if(use_hash) init_wire_iterator(x1, y1, x2, y2); + if(use_hash) init_wire_iterator(&ctx, x1, y1, x2, y2); else i = -1; while(1) { if(use_hash) { - if( !(wireptr = wire_iterator_next())) break; + if( !(wireptr = wire_iterator_next(&ctx))) break; i = wireptr->n; } else { diff --git a/src/hash_iterator.c b/src/hash_iterator.c index 9ec24ac0..5272597b 100644 --- a/src/hash_iterator.c +++ b/src/hash_iterator.c @@ -22,123 +22,107 @@ #include "xschem.h" -static int x1a, x2a; -static int y1a, y2a; -static int i, j, counti, countj; -static int tmpi, tmpj; -static struct instentry *instanceptr; -static struct wireentry *wireptr; -static unsigned short *instflag=NULL; -static unsigned short *wireflag=NULL; - -void init_inst_iterator(double x1, double y1, double x2, double y2) +void init_inst_iterator(struct iterator_ctx *ctx, double x1, double y1, double x2, double y2) { + ctx->instflag = NULL; dbg(3, "init_inst_iterator(): instances=%d\n", xctx->instances); - my_realloc(135, &instflag, xctx->instances*sizeof(unsigned short)); - memset(instflag, 0, xctx->instances*sizeof(unsigned short)); + my_realloc(135, &ctx->instflag, xctx->instances*sizeof(unsigned short)); + memset(ctx->instflag, 0, xctx->instances*sizeof(unsigned short)); /* calculate square 4 1st corner of drawing area */ - x1a=floor(x1/BOXSIZE) ; - y1a=floor(y1/BOXSIZE) ; + ctx->x1a = floor(x1/BOXSIZE) ; + ctx->y1a = floor(y1/BOXSIZE) ; /* calculate square 4 2nd corner of drawing area */ - x2a=floor(x2/BOXSIZE); - y2a=floor(y2/BOXSIZE); - /* printf("init_inst_iterator(): x1a=%d, y1a=%d\n", x1a, y1a); */ - /* printf("init_inst_iterator(): x2a=%d, y2a=%d\n", x2a, y2a); */ - i = x1a; - j = y1a; - tmpi=i%NBOXES; if(tmpi<0) tmpi+=NBOXES; - tmpj=j%NBOXES; if(tmpj<0) tmpj+=NBOXES; - counti=0; - /* printf("init_inst_iterator(): tmpi=%d, tmpj=%d\n", tmpi, tmpj); */ - instanceptr=xctx->insttable[tmpi][tmpj]; - countj=0; + ctx->x2a = floor(x2/BOXSIZE); + ctx->y2a = floor(y2/BOXSIZE); + ctx->i = ctx->x1a; + ctx->j = ctx->y1a; + ctx->tmpi = ctx->i % NBOXES; if(ctx->tmpi<0) ctx->tmpi+=NBOXES; + ctx->tmpj = ctx->j % NBOXES; if(ctx->tmpj<0) ctx->tmpj+=NBOXES; + ctx->counti=0; + ctx->instanceptr=xctx->insttable[ctx->tmpi][ctx->tmpj]; + ctx->countj=0; } -struct instentry *inst_iterator_next() +struct instentry *inst_iterator_next(struct iterator_ctx *ctx) { struct instentry *ptr; dbg(3, "inst_iterator_next(): instances=%d\n", xctx->instances); while(1) { - while(instanceptr) { - ptr = instanceptr; - instanceptr = instanceptr -> next; - if(!instflag[ptr->n]) { - instflag[ptr->n]=1; + while(ctx->instanceptr) { + ptr = ctx->instanceptr; + ctx->instanceptr = ctx->instanceptr->next; + if(!ctx->instflag[ptr->n]) { + ctx->instflag[ptr->n]=1; return ptr; } } - if(jinsttable[tmpi][tmpj]; - } else if(iinsttable[tmpi][tmpj]; + if(ctx->j < ctx->y2a && ctx->countj++ < NBOXES) { + ctx->j++; + ctx->tmpj = ctx->j % NBOXES; if(ctx->tmpj < 0) ctx->tmpj+=NBOXES; + ctx->instanceptr = xctx->insttable[ctx->tmpi][ctx->tmpj]; + } else if(ctx->i < ctx->x2a && ctx->counti++ < NBOXES) { + ctx->i++; + ctx->j = ctx->y1a; + ctx->countj = 0; + ctx->tmpi = ctx->i % NBOXES; if(ctx->tmpi < 0) ctx->tmpi += NBOXES; + ctx->tmpj = ctx->j % NBOXES; if(ctx->tmpj < 0) ctx->tmpj += NBOXES; + ctx->instanceptr = xctx->insttable[ctx->tmpi][ctx->tmpj]; } else { - my_free(753, &instflag); + my_free(753, &ctx->instflag); return NULL; } } } -void init_wire_iterator(double x1, double y1, double x2, double y2) +void init_wire_iterator(struct iterator_ctx *ctx, double x1, double y1, double x2, double y2) { + ctx->wireflag = NULL; dbg(3, "init_wire_iterator(): wires=%d\n", xctx->wires); - my_realloc(136, &wireflag, xctx->wires*sizeof(unsigned short)); - memset(wireflag, 0, xctx->wires*sizeof(unsigned short)); + my_realloc(136, &ctx->wireflag, xctx->wires*sizeof(unsigned short)); + memset(ctx->wireflag, 0, xctx->wires*sizeof(unsigned short)); /* calculate square 4 1st corner of drawing area */ - x1a=floor(x1/BOXSIZE) ; - y1a=floor(y1/BOXSIZE) ; + ctx->x1a = floor(x1 / BOXSIZE) ; + ctx->y1a = floor(y1 / BOXSIZE) ; /* calculate square 4 2nd corner of drawing area */ - x2a=floor(x2/BOXSIZE); - y2a=floor(y2/BOXSIZE); - /* printf("init_wire_iterator(): x1a=%d, y1a=%d\n", x1a, y1a); */ - /* printf("init_wire_iterator(): x2a=%d, y2a=%d\n", x2a, y2a); */ - i = x1a; - j = y1a; - tmpi=i%NBOXES; if(tmpi<0) tmpi+=NBOXES; - tmpj=j%NBOXES; if(tmpj<0) tmpj+=NBOXES; - counti=0; - /* printf("init_inst_iterator(): tmpi=%d, tmpj=%d\n", tmpi, tmpj); */ - wireptr=xctx->wiretable[tmpi][tmpj]; - countj=0; + ctx->x2a = floor(x2 / BOXSIZE); + ctx->y2a = floor(y2 / BOXSIZE); + ctx->i = ctx->x1a; + ctx->j = ctx->y1a; + ctx->tmpi=ctx->i % NBOXES; if(ctx->tmpi < 0) ctx->tmpi += NBOXES; + ctx->tmpj=ctx->j % NBOXES; if(ctx->tmpj < 0) ctx->tmpj += NBOXES; + ctx->counti=0; + ctx->wireptr = xctx->wiretable[ctx->tmpi][ctx->tmpj]; + ctx->countj = 0; } -struct wireentry *wire_iterator_next() +struct wireentry *wire_iterator_next(struct iterator_ctx *ctx) { struct wireentry *ptr; dbg(3, "wire_iterator_next(): wires=%d\n", xctx->wires); while(1) { - while(wireptr) { - ptr = wireptr; - wireptr = wireptr -> next; - if(!wireflag[ptr->n]) { - wireflag[ptr->n]=1; + while(ctx->wireptr) { + ptr = ctx->wireptr; + ctx->wireptr = ctx->wireptr -> next; + if(!ctx->wireflag[ptr->n]) { + ctx->wireflag[ptr->n]=1; return ptr; } } - if(jwiretable[tmpi][tmpj]; - } else if(iwiretable[tmpi][tmpj]; + if(ctx->j < ctx->y2a && ctx->countj++ < NBOXES) { + ctx->j++; + ctx->tmpj = ctx->j % NBOXES; if(ctx->tmpj < 0) ctx->tmpj += NBOXES; + ctx->wireptr = xctx->wiretable[ctx->tmpi][ctx->tmpj]; + } else if(ctx->i < ctx->x2a && ctx->counti++ < NBOXES) { + ctx->i++; + ctx->j = ctx->y1a; + ctx->countj = 0; + ctx->tmpi = ctx->i % NBOXES; if(ctx->tmpi < 0) ctx->tmpi += NBOXES; + ctx->tmpj = ctx->j % NBOXES; if(ctx->tmpj < 0) ctx->tmpj += NBOXES; + ctx->wireptr = xctx->wiretable[ctx->tmpi][ctx->tmpj]; } else { - my_free(754, &wireflag); + my_free(754, &ctx->wireflag); return NULL; } } diff --git a/src/hilight.c b/src/hilight.c index a1923a5e..4bb8592b 100644 --- a/src/hilight.c +++ b/src/hilight.c @@ -1338,6 +1338,117 @@ void select_hilight_net(void) } +/* select all nets and pins/labels that are *physically* connected to current selected wire segments */ +/* Recursive routine */ +static void check_connected_wire(int n) +{ + int k, touches; + xWire * const wire = xctx->wire; + struct wireentry *wireptr; + struct instentry *instptr; + char *type; + double x1, y1, x2, y2; + struct iterator_ctx ctx; + + x1 = wire[n].x1; + y1 = wire[n].y1; + x2 = wire[n].x2; + y2 = wire[n].y2; + RECTORDER(x1, y1, x2, y2); + dbg(1, "check_connected_wire(): n=%d, %g %g %g %g\n", n, x1, y1, x2, y2); + for(init_inst_iterator(&ctx, x1, y1, x2, y2); (instptr = inst_iterator_next(&ctx)) ;) { + k = instptr->n; + type = (xctx->inst[k].ptr+ xctx->sym)->type; + if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe"))) { + double rx1, ry1, x0, y0; + int rot, flip; + xRect *rct; + rct=(xctx->inst[k].ptr+ xctx->sym)->rect[PINLAYER]; + if(rct) { + x0=(rct[0].x1+rct[0].x2)/2; + y0=(rct[0].y1+rct[0].y2)/2; + rot=xctx->inst[k].rot; + flip=xctx->inst[k].flip; + ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); + x0=xctx->inst[k].x0+rx1; + y0=xctx->inst[k].y0+ry1; + touches = touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, x0, y0); + if(touches) { + xctx->need_reb_sel_arr=1; + xctx->inst[k].sel = SELECTED; + } + } + } + } + for(init_wire_iterator(&ctx, x1, y1, x2, y2); (wireptr = wire_iterator_next(&ctx)) ;) { + k = wireptr->n; + if(n == k || xctx->wire[k].sel == SELECTED) continue; + touches = touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, wire[k].x1, wire[k].y1) || + touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, wire[k].x2, wire[k].y2) || + touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, wire[n].x1, wire[n].y1) || + touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, wire[n].x2, wire[n].y2); + if(touches) { + xctx->need_reb_sel_arr=1; + xctx->wire[k].sel = SELECTED; + check_connected_wire(k); /* recursive check */ + } + } +} + +void select_connected_wires(void) +{ + int i, n; + hash_wires(); + hash_instances(); + + rebuild_selected_array(); /* does nothing as already done in most of use cases */ + for(n=0; nlastsel; n++) { + i = xctx->sel_array[n].n; + switch(xctx->sel_array[n].type) { + char *type; + case WIRE: + if(xctx->wire[i].sel == SELECTED) check_connected_wire(i); + break; + case ELEMENT: + type = (xctx->inst[i].ptr+ xctx->sym)->type; + if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe"))) { + double rx1, ry1, x0, y0; + int rot, flip, sqx, sqy; + xRect *rct; + struct wireentry *wptr; + rct = (xctx->inst[i].ptr+ xctx->sym)->rect[PINLAYER]; + if(rct) { + x0 = (rct[0].x1 + rct[0].x2) / 2; + y0 = (rct[0].y1 + rct[0].y2) / 2; + rot = xctx->inst[i].rot; + flip = xctx->inst[i].flip; + ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1); + x0 = xctx->inst[i].x0+rx1; + y0 = xctx->inst[i].y0+ry1; + get_square(x0, y0, &sqx, &sqy); + wptr = xctx->wiretable[sqx][sqy]; + while (wptr) { + dbg(1, "select_connected_wires(): x0=%g y0=%g wire[%d]=%g %g %g %g\n", + x0, y0, wptr->n, xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, + xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2); + if (touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1, + xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) { + xctx->wire[wptr->n].sel = SELECTED; + check_connected_wire(wptr->n); + } + wptr=wptr->next; + } + } /* if(rct) */ + } /* if(type & ...) */ + break; + default: + break; + } /* switch(...) */ + } /* for(... lastsel ...) */ + rebuild_selected_array(); + draw_selection(gc[SELLAYER], 0); +} + void draw_hilight_net(int on_window) { int save_draw; @@ -1348,6 +1459,7 @@ void draw_hilight_net(int on_window) struct wireentry *wireptr; struct instentry *instanceptr; struct hilight_hashentry *entry; + struct iterator_ctx ctx; if(!xctx->hilight_nets) return; dbg(3, "draw_hilight_net(): xctx->prep_hi_structs=%d\n", xctx->prep_hi_structs); @@ -1363,11 +1475,11 @@ void draw_hilight_net(int on_window) hash_wires(); hash_instances(); } - if(use_hash) init_wire_iterator(x1, y1, x2, y2); + if(use_hash) init_wire_iterator(&ctx, x1, y1, x2, y2); else i = -1; while(1) { if(use_hash) { - if( !(wireptr = wire_iterator_next())) break; + if( !(wireptr = wire_iterator_next(&ctx))) break; i = wireptr->n; } else { @@ -1393,11 +1505,11 @@ void draw_hilight_net(int on_window) } for(c=0;cn; } else { diff --git a/src/keys.help b/src/keys.help index a2ac3e7d..fe04d7bc 100644 --- a/src/keys.help +++ b/src/keys.help @@ -44,6 +44,7 @@ LeftButton Double click Terminate Polygon placement ---------------------------------------------------------------------- - BackSpace Back to parent schematic - Delete Delete selected objects +shift Delete select all connected wires/labels/probes - Insert Insert element from library - Down Move down ctrl Enter Confirm closing dialog boxes @@ -60,6 +61,10 @@ ctrl Enter Confirm closing dialog boxes ctrl '#' Rename components with duplicated name (refdes) - '5' View only probes ctrl '0-9' set current layer (4 -13) + '0' set selected net or label to logic value '0' + '1' set selected net or label to logic value '1' + '2' set selected net or label to logic value 'X' + '3' toggle selected net or label: 1->0, 0->1, X->X - 'a' Make symbol from pin list of current schematic ctrl 'a' Select all shift 'A' Toggle show netlist @@ -106,6 +111,7 @@ alt 'k' Select all nets attached to selected wire / label / pin. ctrl 'l' Make schematic view from selected symbol alt+shift 'l' add lab_wire.sym to schematic alt 'l' add lab_pin.sym to schematic +ctrl+shift 'o' Load most recent schematic ctrl 'o' Load schematic - 'm' Move selected obj. shift 'N' Hierarchical netlist diff --git a/src/psprint.c b/src/psprint.c index 19ce4219..e8b5534f 100644 --- a/src/psprint.c +++ b/src/psprint.c @@ -747,13 +747,14 @@ void ps_draw(void) double x1, y1, x2, y2; struct wireentry *wireptr; int i; + struct iterator_ctx ctx; update_conn_cues(0, 0); /* draw connecting dots */ x1 = X_TO_XSCHEM(xctx->areax1); y1 = Y_TO_XSCHEM(xctx->areay1); x2 = X_TO_XSCHEM(xctx->areax2); y2 = Y_TO_XSCHEM(xctx->areay2); - for(init_wire_iterator(x1, y1, x2, y2); ( wireptr = wire_iterator_next() ) ;) { + for(init_wire_iterator(&ctx, x1, y1, x2, y2); ( wireptr = wire_iterator_next(&ctx) ) ;) { i = wireptr->n; if( xctx->wire[i].end1 >1 ) { /* 20150331 draw_dots */ ps_drawarc(WIRELAYER, 1, xctx->wire[i].x1, xctx->wire[i].y1, cadhalfdotsize, 0, 360, 0); diff --git a/src/scheduler.c b/src/scheduler.c index 5934f56d..2b490cf0 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -268,6 +268,13 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg } } + else if(!strcmp(argv[1],"connected_nets")) /* selected nets connected to currently selected ones */ + { + cmd_found = 1; + select_connected_wires(); + Tcl_ResetResult(interp); + } + else if(!strcmp(argv[1],"copy")) { cmd_found = 1; diff --git a/src/svgdraw.c b/src/svgdraw.c index dda6d5de..f9a28474 100644 --- a/src/svgdraw.c +++ b/src/svgdraw.c @@ -742,13 +742,14 @@ void svg_draw(void) double x1, y1, x2, y2; struct wireentry *wireptr; int i; + struct iterator_ctx ctx; update_conn_cues(0, 0); /* draw connecting dots */ x1 = X_TO_XSCHEM(xctx->areax1); y1 = Y_TO_XSCHEM(xctx->areay1); x2 = X_TO_XSCHEM(xctx->areax2); y2 = Y_TO_XSCHEM(xctx->areay2); - for(init_wire_iterator(x1, y1, x2, y2); ( wireptr = wire_iterator_next() ) ;) { + for(init_wire_iterator(&ctx, x1, y1, x2, y2); ( wireptr = wire_iterator_next(&ctx) ) ;) { i = wireptr->n; color = WIRELAYER; if(xctx->hilight_nets && (entry=bus_hilight_lookup( xctx->wire[i].node, 0, XLOOKUP))) { diff --git a/src/xschem.h b/src/xschem.h index 728f4c3e..076605a7 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -476,6 +476,18 @@ typedef struct double zoom; } Zoom; + +struct iterator_ctx { + int x1a, x2a; + int y1a, y2a; + int i, j, counti, countj; + int tmpi, tmpj; + struct instentry *instanceptr; + struct wireentry *wireptr; + unsigned short *instflag; + unsigned short *wireflag; + }; + struct simdata_pin { char *function; char *go_to; @@ -1042,10 +1054,10 @@ extern void tclsetvar(const char *s, const char *value); extern void tcl_hook(char **res); extern void statusmsg(char str[],int n); extern void place_text(int draw_text, double mx, double my); -extern void init_inst_iterator(double x1, double y1, double x2, double y2); -extern struct instentry *inst_iterator_next(); -extern void init_wire_iterator(double x1, double y1, double x2, double y2); -extern struct wireentry *wire_iterator_next(); +extern void init_inst_iterator(struct iterator_ctx *ctx, double x1, double y1, double x2, double y2); +extern struct instentry *inst_iterator_next(struct iterator_ctx *ctx); +extern void init_wire_iterator(struct iterator_ctx *ctx, double x1, double y1, double x2, double y2); +extern struct wireentry *wire_iterator_next(struct iterator_ctx *ctx); extern void check_unique_names(int rename); extern void clear_instance_hash(); @@ -1137,6 +1149,7 @@ extern void logic_set(int v, int num); extern int hilight_netname(const char *name); extern void unhilight_net(); extern void propagate_hilights(int set, int clear, int mode); +extern void select_connected_wires(void); extern void draw_hilight_net(int on_window); extern void display_hilights(char **str); extern void redraw_hilights(void); diff --git a/src/xschem.tcl b/src/xschem.tcl index 52b8e452..f830abce 100644 --- a/src/xschem.tcl +++ b/src/xschem.tcl @@ -4044,6 +4044,8 @@ if { ( $::OS== "Windows" || [string length [lindex [array get env DISPLAY] 1] ] toolbar_create ToolBreak "xschem break_wires" "Break Wires" .menubar.tools.menu add checkbutton -label "Auto Join/Trim Wires" -variable autotrim_wires \ -command { xschem set autotrim_wires $autotrim_wires} + .menubar.tools.menu add command -label "Select all connected wires/labels/pins" -accelerator {Shift-Delete} \ + -command { xschem connected_nets} .menubar.hilight.menu add command -label {Highlight net-pin name mismatches on selected instancs} \ -command "xschem net_pin_mismatch" \ diff --git a/xschem_library/devices/ngspice_probe.sym b/xschem_library/devices/ngspice_probe.sym index 0336b64e..93ed0ba2 100644 --- a/xschem_library/devices/ngspice_probe.sym +++ b/xschem_library/devices/ngspice_probe.sym @@ -1,6 +1,6 @@ -v {xschem version=2.9.8 file_version=1.2} +v {xschem version=2.9.9 file_version=1.2 } G {} -K {type=raw_data_show +K {type=probe vhdl_ignore=true spice_ignore=false verilog_ignore=true