From 34001d7ff0599511f4228a571aef59b129ec14cc Mon Sep 17 00:00:00 2001
From: stefan schippers <stefan.schippers@gmail.com>
Date: Tue, 23 Sep 2025 08:19:37 +0200
Subject: [PATCH] improve tb_diff_amp.sch testcase

---
 xschem_library/ngspice/diff_amp.sym    |  5 +++--
 xschem_library/ngspice/diff_amp.va     | 21 +++++++++++++++++++++
 xschem_library/ngspice/tb_diff_amp.sch | 14 ++++++++++----
 3 files changed, 34 insertions(+), 6 deletions(-)
 create mode 100644 xschem_library/ngspice/diff_amp.va

diff --git a/xschem_library/ngspice/diff_amp.sym b/xschem_library/ngspice/diff_amp.sym
index 93676b81..ffa02cd9 100644
--- a/xschem_library/ngspice/diff_amp.sym
+++ b/xschem_library/ngspice/diff_amp.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.6 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -28,7 +28,7 @@ template="name=X1 model=diff_amp_cell gain=40 amplitude=3 offset=1.5"
 device_model="tcleval(
 .control
 * following line specifies the location for the .osdi file so ngspice can use it.
-pre_osdi $USER_CONF_DIR/xschem_library/diff_amp.osdi
+pre_osdi [abs_sym_path diff_amp.osdi]
 .endc
 
 .model diff_amp_model diff_amp $ gain=40 amplitude=3 offset=1.5
@@ -40,6 +40,7 @@ N1 out in1 in2 diff_amp_model gain=gain amplitude=amplitude offset=offset
 }
 V {}
 S {}
+F {}
 E {}
 L 4 -100 -40 -80 -40 {}
 L 4 80 0 100 0 {}
diff --git a/xschem_library/ngspice/diff_amp.va b/xschem_library/ngspice/diff_amp.va
new file mode 100644
index 00000000..7be92a84
--- /dev/null
+++ b/xschem_library/ngspice/diff_amp.va
@@ -0,0 +1,21 @@
+// importing libs
+`include "discipline.h"
+
+module diff_amp(
+  output electrical out, 
+  input electrical in1,
+  input electrical in2);
+
+(* desc="gain", units="", type="instance" *)   parameter real gain = 40 from [-inf: inf];
+(* desc="amplitude", units="", type="instance" *)    parameter real amplitude = 3 from [-inf: inf];
+(* desc="offset", units="", type="instance" *) parameter real offset = 1.5 from [-inf: inf];
+
+analog begin
+
+    V(out) <+ offset + amplitude / 2 * tanh( gain / amplitude * 2 * V(in1, in2));
+
+end
+endmodule
+
+
+
diff --git a/xschem_library/ngspice/tb_diff_amp.sch b/xschem_library/ngspice/tb_diff_amp.sch
index 3d02e9a5..81e8f0e3 100644
--- a/xschem_library/ngspice/tb_diff_amp.sch
+++ b/xschem_library/ngspice/tb_diff_amp.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.6 file_version=1.2
+v {xschem version=3.4.8RC file_version=1.3
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -23,6 +23,7 @@ G {}
 K {}
 V {}
 S {}
+F {}
 E {}
 B 2 840 -580 1640 -170 {flags=graph
 y1=6.3e-14
@@ -89,8 +90,7 @@ analog begin
 end
 endmodule
 } 40 -870 0 0 0.2 0.2 {font=monospace}
-T {create a diff_amp.va file with following code 
-and compile it into a .osdi file with openvaf.} 190 -940 0 0 0.4 0.4 {}
+T {This symbol is described by a diff_amp.va Verilog-A file} 100 -920 0 0 0.4 0.4 {}
 N 180 -450 320 -450 {lab=B}
 N 80 -530 320 -530 {lab=A}
 N 520 -490 640 -490 {lab=Z}
@@ -128,4 +128,10 @@ C {launcher.sym} 670 -170 0 0 {name=h1
 descr="OP annotate" 
 tclcommand="xschem annotate_op"
 }
-C {diff_amp.sym} 420 -490 0 0 {name=X1 model=diff_amp_cell gain=100 amplitude=5 offset=2.5}
+C {diff_amp.sym} 420 -490 0 0 {name=X1 model=diff_amp_cell gain=100 amplitude=5 offset=2.5
+tclcommand="edit_file [abs_sym_path diff_amp.va]"}
+C {launcher.sym} 450 -390 0 0 {name=h2
+descr="Compile Verilog-A file" 
+
+tclcommand="execute 1 sh -c \\" openvaf [abs_sym_path diff_amp.va] \\"  "
+}