diff --git a/src/netlist.c b/src/netlist.c
index 17463c0e..512b94c0 100644
--- a/src/netlist.c
+++ b/src/netlist.c
@@ -1726,7 +1726,8 @@ int sym_vs_sch_pins(int all)
               break;
             case 'C':
               load_ascii_string(&tmp, fd);
-              my_strncpy(name, tmp, S(name));
+              /* my_strncpy(name, tmp, S(name)); */
+              my_strncpy(name, tcl_hook2(tmp), S(name));
 
               if(!strcmp(f_version,"1.0") ) {
                 dbg(1, "sym_vs_sch_pins(): add_ext(name,\".sym\") = %s\n", add_ext(name, ".sym") );
diff --git a/xschem_library/ngspice/comp_ngspice.sch b/xschem_library/ngspice/comp_ngspice.sch
index b2d46904..bea695a2 100644
--- a/xschem_library/ngspice/comp_ngspice.sch
+++ b/xschem_library/ngspice/comp_ngspice.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.6RC file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -43,7 +43,7 @@ C {lab_pin.sym} 450 -120 0 0 {name=p35 lab=0}
 C {bsource.sym} 450 -150 0 1 {name=B1 VAR=V FUNC="\{OFFSET + AMPLITUDE/2*(tanh(V(IPLUS,IMINUS)*GAIN*2/AMPLITUDE))\}"
 }
 C {title.sym} 160 -30 0 0 {name=l3 author="Stefan Schippers"}
-C {res.sym} 570 -240 1 0 {name=R1
+C {tcleval(res.sym)} 570 -240 1 0 {name=R1
 value=\{ROUT\}
 m=1}
 C {parax_cap.sym} 630 -230 0 0 {name=C3 gnd=0 value=\{COUT\} m=1}