From 28cc187b5655911cf1cb90eef91aa1009587cc65 Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Thu, 9 Jun 2022 09:32:34 +0200
Subject: [PATCH] when placing components with lock=true set in template
 attribute allow to move it to its final position like any other unlocked
 symbol. Code in place in verilog.awk to do bit unblasting in net-> port
 associations, but not enalbed it for now as icarus verilog does not handle
 some bus slices (for example if bus slice direction is different from
 declared bus direction)

---
 src/actions.c                      |  2 +-
 src/verilog.awk                    | 86 ++++++++++++++++++++++++++----
 xschem_library/devices/title-2.sym |  7 +--
 3 files changed, 82 insertions(+), 13 deletions(-)

diff --git a/src/actions.c b/src/actions.c
index f8965dc1..cb626bf3 100644
--- a/src/actions.c
+++ b/src/actions.c
@@ -1085,7 +1085,7 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
   /*   hilight new element 24122002 */
 
   if(draw_sym & 4 ) {
-    select_element(n, SELECTED,0, 0);
+    select_element(n, SELECTED,0, 1);
     drawtemparc(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0, 0.0);
     drawtemprect(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0);
     drawtempline(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0);
diff --git a/src/verilog.awk b/src/verilog.awk
index c1fa5c2b..3ab7e32a 100755
--- a/src/verilog.awk
+++ b/src/verilog.awk
@@ -268,15 +268,21 @@ begin_module && $1 ~/^\);$/ {
     }
     if(nmult==1) printf "\n .%s( %s )" ,s_b($(j-1)),pin
     else {
-     split(pin,pin_array,",")
-     basename=s_b(pin_array[1])
-     if(check2(pin_array,nmult) && net_ascending==0) {  ## 20140416 if ascending nets print single bits
-      if(nmult==signal_basename[basename] )
-        printf "\n .%s( %s )", s_b($(j-1)),basename
-      else
-        printf "\n .%s( %s[%s:%s] )",s_b($(j-1)),basename,s_i(pin_array[1]),s_i(pin_array[nmult])
-     }
-     else printf "\n .%s( %s )", s_b($(j-1)), (nmult>1? "{" pin "}" : pin)
+      # old code
+      if(1) {
+        split(pin,pin_array,",")
+        basename=s_b(pin_array[1])
+        if(check2(pin_array,nmult) && net_ascending==0) {  ## 20140416 if ascending nets print single bits
+         if(nmult==signal_basename[basename] )
+           printf "\n .%s( %s )", s_b($(j-1)),basename
+         else
+           printf "\n .%s( %s[%s:%s] )",s_b($(j-1)),basename,s_i(pin_array[1]),s_i(pin_array[nmult])
+        }
+        else printf "\n .%s( %s )", s_b($(j-1)), (nmult>1? "{" pin "}" : pin)
+      # new code
+      } else {
+        printf "\n .%s( %s )" ,s_b($(j-1)),compact_label(pin)
+      }
     }
    }
    printf "\n);\n\n"
@@ -463,6 +469,68 @@ function check(arr,n      ,i,start,ok)
  return 1
 }
 
+
+# globals: newlab, startbus, startsig
+function compact_label(lab,      n, i, last, lab_array, bus_current, name, busname)
+{
+  n=split(lab,lab_array,",")
+  startbus=-1
+  startsig=-1
+  newlab=""
+  for(i=1;i<=n;i++) {
+   if(lab_array[i] ~ /\[/) {
+     bus_current=s_i(lab_array[i])
+
+     if( startsig!=-1 &&  lab_array[i] != name )
+         print_signal(name)
+     if( (startbus!=-1) && (s_b(lab_array[i]) != busname) )
+         print_bus(busname, last)
+     # 09032004 fix for errors on buses like D[5],D[4],D[2],D[1]
+     if( (startbus!=-1) && (s_b(lab_array[i]) == busname) && ((bus_current+1!=last) && (bus_current-1!=last)) )
+         print_bus(busname, last)
+
+     if(startbus==-1) { busname=s_b(lab_array[i]); startbus=bus_current; last=bus_current }
+     else if(s_b(lab_array[i])==busname && ((bus_current+1==last) || (bus_current-1==last)) ) { last=bus_current }
+
+     if( (startbus!=-1) && i==n )
+         print_bus(busname, last)
+   }
+   else {
+     if(s_b(lab_array[i]) != busname&& startbus!=-1)
+       print_bus(busname, last)
+     if( (startsig!=-1) && ( lab_array[i] != name) )
+       print_signal(name)
+
+     if(startsig==-1) { name=lab_array[i] ; startsig++ }
+     else if(lab_array[i] == name) { startsig++ }
+
+     if( (startsig!=-1) && i==n )
+       print_signal(name)
+   }
+  }
+  sub(/,$/,"",newlab)
+  if(newlab ~ /,/) newlab="{" newlab "}"
+  return newlab
+}
+
+function print_bus(busname, last) {
+   if(startbus!=last)
+       newlab=newlab busname "[" startbus ":" last "],"
+   else
+       newlab=newlab busname "[" startbus "],"
+   startbus=-1
+}
+
+function print_signal(name,       i) {
+   if(startsig>0) {
+      # newlab = newlab startsig+1 "*" name ","
+      for(i = 0; i <= startsig; i++)  newlab = newlab name ","
+   } else
+      newlab = newlab name ","
+   startsig=-1
+}
+
+
 function s_b(n)
 {
  sub(/\[.*/,"",n)
diff --git a/xschem_library/devices/title-2.sym b/xschem_library/devices/title-2.sym
index d8c39b4d..c15bf315 100644
--- a/xschem_library/devices/title-2.sym
+++ b/xschem_library/devices/title-2.sym
@@ -1,11 +1,12 @@
-v {xschem version=2.9.7 file_version=1.2}
+v {xschem version=3.0.0 file_version=1.2 }
 G {}
 K {type=logo
-template="name=l1 author=\\"Stefan Schippers\\" rev=1.0"
+template="name=l1 author=\\"Stefan Schippers\\" rev=1.0 lock=true"
 verilog_ignore=true
 vhdl_ignore=true
 spice_ignore=true
-tedax_ignore=true}
+tedax_ignore=true
+}
 V {}
 S {}
 E {}