diff --git a/doc/xschem_man/graphs.html b/doc/xschem_man/graphs.html
index d58c1e3b..0f2f929d 100644
--- a/doc/xschem_man/graphs.html
+++ b/doc/xschem_man/graphs.html
@@ -161,6 +161,7 @@ p{padding: 15px  30px 10px;}
   <li><kbd>**</kbd> Exponentiation</li>
   <li><kbd>exch()</kbd> Exchange top 2 operands on stack</li>
   <li><kbd>ravg()</kbd> Running average of over a specified time window</li>
+  <li><kbd>del()</kbd> Delete waveform by specified quantity on the X-axis</li>
   </ul>
   <p>1 argument operators:</p>
   <ul>
@@ -173,7 +174,9 @@ p{padding: 15px  30px 10px;}
   <li><kbd>exp()</kbd> Base-e Exponentiation</li>
   <li><kbd>ln()</kbd> Base-e logarithm</li>
   <li><kbd>log10()</kbd> Base 10 logarithm</li>
-  <li><kbd>avg()</kbd> Moving average</li>
+  <li><kbd>db20()</kbd> Value in deciBel (20 * log10(n))</li>
+  <li><kbd>avg()</kbd> Average</li>
+  <li><kbd>prev()</kbd> Delete waveform by one point (at any x-axis position take the previous value)</li>
   <li><kbd>deriv()</kbd> Derivative w.r.t. graph sweep variable</li>
   <li><kbd>deriv0()</kbd> Derivative w.r.t. simulation (index 0) sweep variable</li>
   <li><kbd>integ()</kbd> Integration</li>
diff --git a/src/save.c b/src/save.c
index b5ec9182..3eba6d92 100644
--- a/src/save.c
+++ b/src/save.c
@@ -810,7 +810,7 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr)
             /* dbg(0, "p=%d, x[p]=%g\n", p, x[p]);  */
             tmp = stack2[stackptr2 - 1];
             ravg_store(1, i, p, last, stack2[stackptr2 - 2]);
-            if(fabs(x[p] - x[first]) < tmp) {
+            if(fabs(x[p] - x[first]) <= tmp) {
               result = stack2[stackptr2 - 2];
               stack1[i].prevp = first;
             } else {
diff --git a/src/token.c b/src/token.c
index 558ffdff..983170a0 100644
--- a/src/token.c
+++ b/src/token.c
@@ -1462,14 +1462,15 @@ void print_verilog_param(FILE *fd, int symbol)
  int quote=0;
  int escape=0;
  int token_number=0;
+ char *extra = NULL;
 
  my_strdup(479, &template, xctx->sym[symbol].templ); /* 20150409 20171103 */
- my_strdup(480, &generic_type, get_tok_value(xctx->sym[symbol].prop_ptr,"generic_type",0));
  if( !template || !(template[0]) )  {
    my_free(1006, &template);
-   my_free(1007, &generic_type);
    return;
  }
+ my_strdup(480, &generic_type, get_tok_value(xctx->sym[symbol].prop_ptr,"generic_type",0));
+ my_strdup(1558, &extra, get_tok_value(xctx->sym[symbol].prop_ptr,"extra",0) );
  dbg(2, "print_verilog_param(): symbol=%d template=%s \n", symbol, template);
 
  s=template;
@@ -1511,9 +1512,8 @@ void print_verilog_param(FILE *fd, int symbol)
 
    if(value[0] != '\0') /* token has a value */
    {
-    if(token_number>1)
+    if(token_number>1 && (!extra || !strstr(extra, token)))
     {
-
       /* 20080915 put "" around string params */
       if( !generic_type || strcmp(get_tok_value(generic_type,token, 0), "time")  ) {
         if( generic_type && !strcmp(get_tok_value(generic_type,token, 0), "string")  ) {
@@ -1536,6 +1536,7 @@ void print_verilog_param(FILE *fd, int symbol)
  my_free(1009, &generic_type);
  my_free(1010, &value);
  my_free(1011, &token);
+ my_free(1007, &extra);
 }
 
 
@@ -2507,7 +2508,8 @@ void print_verilog_element(FILE *fd, int inst)
  int no_of_pins=0;
  int  tmp1 = 0;
  register int c, state=TOK_BEGIN, space;
- char *value=NULL,  *token=NULL;
+ char *value=NULL,  *token=NULL, *extra = NULL;
+ char *extra_ptr, *saveptr1, *extra_token;
  size_t sizetok=0, sizeval=0;
  size_t token_pos=0, value_pos=0;
  int quote=0;
@@ -2518,16 +2520,15 @@ void print_verilog_element(FILE *fd, int inst)
   print_verilog_primitive(fd, inst);
   return;
  }
- my_strdup(506, &template,
-     (xctx->inst[inst].ptr + xctx->sym)->templ);
 
  my_strdup(507, &name,xctx->inst[inst].instname);
  if(!name) my_strdup(3, &name, get_tok_value(template, "name", 0));
  if(name==NULL) {
-   my_free(1040, &template);
    my_free(1041, &name);
    return;
  }
+ my_strdup(1559, &extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "extra", 0));
+ my_strdup(506, &template, (xctx->inst[inst].ptr + xctx->sym)->templ);
  no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
 
  /* 20080915 use generic_type property to decide if some properties are strings, see later */
@@ -2573,7 +2574,7 @@ void print_verilog_element(FILE *fd, int inst)
    value[value_pos]='\0';
    value_pos=0;
    get_tok_value(template, token, 0);
-   if(strcmp(token, "name") && xctx->tok_size) {
+   if(strcmp(token, "name") && xctx->tok_size && (!extra || !strstr(extra, token))) {
      if(value[0] != '\0') /* token has a value */
      {
        if(strcmp(token,"spice_ignore") && strcmp(token,"vhdl_ignore") && strcmp(token,"tedax_ignore")) {
@@ -2624,6 +2625,22 @@ void print_verilog_element(FILE *fd, int inst)
      }
    }
  }
+
+ if(extra) {
+   const char *val;
+   for(extra_ptr = extra; ; extra_ptr=NULL) {
+     extra_token=my_strtok_r(extra_ptr, " ", "", &saveptr1);
+     if(!extra_token) break;
+
+     val = get_tok_value(xctx->inst[inst].prop_ptr, extra_token, 0);
+     if(!val[0]) val = get_tok_value( (xctx->inst[inst].ptr + xctx->sym)->prop_ptr, extra_token, 0);
+     if(tmp) fprintf(fd,"\n");
+     fprintf(fd, "  ?%d %s %s ", 1, extra_token, val);
+     tmp = 1;
+   }
+ }
+
+
  fprintf(fd, "\n);\n\n");
  dbg(2, "print_verilog_element(): ------- end ------ \n");
  my_free(1042, &name);
@@ -2631,6 +2648,7 @@ void print_verilog_element(FILE *fd, int inst)
  my_free(1044, &template);
  my_free(1045, &value);
  my_free(1046, &token);
+ my_free(1560, &extra);
 }
 
 
diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c
index 8a0e0481..8223c669 100644
--- a/src/verilog_netlist.c
+++ b/src/verilog_netlist.c
@@ -424,6 +424,8 @@ void verilog_block_netlist(FILE *fd, int i)
   const char *str_tmp, *fmt_attr = NULL;
   int split_f;
   const char *sym_def;
+  char *extra_ptr, *saveptr1, *extra_token, *extra = NULL, *extra2=NULL;
+
 
   split_f = tclgetboolvar("split_files");
   if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"verilog_stop",0),"true") )
@@ -447,6 +449,8 @@ void verilog_block_netlist(FILE *fd, int i)
   if(sym_def[0]) {
     fprintf(fd, "%s\n", sym_def);
   } else {
+    my_strdup(1040, &extra, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "extra", 0));
+    my_strdup(1563, &extra2, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "extra", 0));
     fprintf(fd, "// sch_path: %s\n", filename);
     verilog_stop? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
     /* print verilog timescale  and preprocessor directives 10102004 */
@@ -472,7 +476,7 @@ void verilog_block_netlist(FILE *fd, int i)
   
     dbg(1, "verilog_block_netlist():       entity ports\n");
   
-    /* print ports directions */
+    /* print port list */
     tmp=0;
     for(j=0;j<xctx->sym[i].rects[PINLAYER];j++)
     {
@@ -483,14 +487,22 @@ void verilog_block_netlist(FILE *fd, int i)
         fprintf(fd,"  %s", str_tmp ? str_tmp : "<NULL>");
       }
     }
+  
+    if(extra) {
+      for(extra_ptr = extra; ; extra_ptr=NULL) {
+        extra_token=my_strtok_r(extra_ptr, " ", "", &saveptr1);
+        if(!extra_token) break;
+        if(tmp) fprintf(fd, " ,\n");
+        fprintf(fd, "  %s", extra_token);
+        tmp++;
+      }
+    }
     fprintf(fd, "\n);\n");
-  
-  
+
     dbg(1, "verilog_block_netlist():       entity generics\n");
     /* print module  default parameters */
     print_verilog_param(fd,i);
     /* print port types */
-    tmp=0;
     for(j=0;j<xctx->sym[i].rects[PINLAYER];j++)
     {
       if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
@@ -516,7 +528,15 @@ void verilog_block_netlist(FILE *fd, int i)
         fprintf(fd," ;\n");
       }
     }
-  
+    if(extra2) {
+      saveptr1 = NULL;
+      for(extra_ptr = extra2; ; extra_ptr=NULL) {
+        extra_token=my_strtok_r(extra_ptr, " ", "", &saveptr1);
+        if(!extra_token) break;
+        fprintf(fd, "  inout %s ;\n", extra_token);
+        fprintf(fd, "  wire %s ;\n", extra_token);
+      }
+    }
     dbg(1, "verilog_block_netlist():       netlisting %s\n", skip_dir( xctx->sch[xctx->currsch]));
     verilog_netlist(fd, verilog_stop);
     fprintf(fd,"---- begin user architecture code\n");
@@ -545,6 +565,8 @@ void verilog_block_netlist(FILE *fd, int i)
     my_free(1081, &port_value);
     my_free(1082, &type);
     my_free(1083, &tmp_string);
+    my_free(1561, &extra);
+    my_free(1564, &extra2);
   } /* if(!sym_def[0]) */
   if(split_f) {
     int save;