From 215114fce362c908a3ede22cf055a2cbaf2bfff1 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Mon, 5 Feb 2024 12:08:10 +0100 Subject: [PATCH] update symbol property syntax docs with new attribute verilog_extra_dir --- doc/xschem_man/symbol_property_syntax.html | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/doc/xschem_man/symbol_property_syntax.html b/doc/xschem_man/symbol_property_syntax.html index b0f8754d..4a7a49fa 100644 --- a/doc/xschem_man/symbol_property_syntax.html +++ b/doc/xschem_man/symbol_property_syntax.html @@ -367,12 +367,21 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1

You may assign the following attributes to an instance: name=X1 VPWR=VCC VGND=GND subckt=NOR2_1 - and you want to have VCC and GND connections to the symbol in the Verilog netlist but do not want - any of these attributes to be - passed as symbol parameters. In this case you set: verilog_extra="VPWR VGND" and - extra="VPWR VGND subckt" since subckt is probably a spice attribute and you don't - want it in verilog. + and you want to have VCC and GND connections to the symbol in the Verilog netlist but do not want + any of these attributes to be + passed as symbol parameters. In this case you set: verilog_extra="VPWR VGND" and + extra="VPWR VGND subckt" since subckt is probably a spice attribute and you don't + want it in verilog.

+ +
  • verilog_extra_dir
    • +

    + This attribute allows to define the pin directions of verilog_extra symbol ports. + If unspecified the default is + inout. Allowed values are input, output, inout.
    + Example: verilog_extra_dir="VPWR=input VGND=input" +

    +
  • verilogprefix

    • If this attribute is defined in symbol it will be used as a prefix to the symbol name and subcircuit