diff --git a/xschem_library/devices/short.sym b/xschem_library/devices/short.sym
index 1545a727..3de083c0 100644
--- a/xschem_library/devices/short.sym
+++ b/xschem_library/devices/short.sym
@@ -27,9 +27,9 @@ highlight=true}
 V {}
 S {}
 E {}
-L 1 -30 -0 30 0 {}
-B 5 -32.5 -2.5 -27.5 2.5 {name=A dir=inout }
-B 5 27.5 -2.5 32.5 2.5 {name=A dir=inout }
-T {short} 2.5 14 0 0 0.3 0.3 { layer=3
+L 1 0 -30 0 30 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=A dir=inout }
+B 5 -2.5 27.5 2.5 32.5 {name=A dir=inout }
+T {short} 22.5 -26 0 0 0.3 0.3 { layer=3
 hcenter=true}
-T {@name} 15 -22 0 0 0.2 0.2 {}
+T {@name} 5 8 0 0 0.2 0.2 {}
diff --git a/xschem_library/examples/test_lvs_ignore.sch b/xschem_library/examples/test_lvs_ignore.sch
index 81a9145c..9b823c19 100644
--- a/xschem_library/examples/test_lvs_ignore.sch
+++ b/xschem_library/examples/test_lvs_ignore.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -44,7 +44,7 @@ Options->Show net names on symbol pins
 is enabled.} 220 -350 0 0 0.4 0.4 {}
 T {This component has
 attribute
-lvs_ignore=open} 470 -620 0 0 0.4 0.4 {}
+lvs_ignore=open} 470 -650 0 0 0.4 0.4 {}
 N 850 -430 1010 -430 {
 lab=#net1}
 N 850 -430 850 -380 {
@@ -52,13 +52,13 @@ lab=#net1}
 N 50 -540 50 -530 {
 lab=VDD}
 N 50 -470 50 -430 {
-lab=VDD}
+lab=#net2}
 N 50 -430 280 -430 {
-lab=VDD}
+lab=#net2}
 N 360 -430 430 -430 {
 lab=STARTUP}
 N 50 -430 50 -380 {
-lab=VDD}
+lab=#net2}
 N 50 -320 50 -290 {
 lab=GND}
 N 850 -580 850 -570 {
@@ -66,7 +66,7 @@ lab=VDD}
 N 850 -510 850 -430 {
 lab=#net1}
 N 1090 -430 1110 -430 {
-lab=#net2}
+lab=#net3}
 N 850 -320 850 -290 {
 lab=GND}
 N 400 -520 490 -520 {
@@ -74,7 +74,7 @@ lab=STARTUP}
 N 400 -520 400 -430 {
 lab=STARTUP}
 N 550 -520 700 -520 {
-lab=#net3}
+lab=STARTUP}
 C {title.sym} 160 -30 0 0 {name=l1
 author="tcleval([
   if \{$show_pin_net_names == 0\} \{
@@ -126,5 +126,5 @@ device=resistor
 m=1
 }
 C {vdd.sym} 850 -580 0 0 {name=l6 lab=VDD}
-C {short.sym} 520 -520 0 0 {name=x1 value=0.1 lvs_ignore=open}
+C {short.sym} 520 -520 1 0 {name=x1 value=0.1 lvs_ignore=open}
 C {lab_show.sym} 700 -520 0 1 {name=l2 }
diff --git a/xschem_library/examples/test_short_option.sch b/xschem_library/examples/test_short_option.sch
index f7bcc98c..e22f88cb 100644
--- a/xschem_library/examples/test_short_option.sch
+++ b/xschem_library/examples/test_short_option.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -47,41 +47,41 @@ depending on IGNORE} 1310 -540 0 0 0.4 0.4 { layer=1}
 N 130 -290 180 -290 {
 lab=NET_A}
 N 480 -290 530 -290 {
-lab=NET_B}
+lab=NET_A}
 N 180 -390 180 -290 {
 lab=NET_A}
 N 480 -390 480 -290 {
-lab=NET_B}
+lab=NET_A}
 N 180 -390 300 -390 {
 lab=NET_A}
 N 360 -390 480 -390 {
-lab=NET_B}
+lab=NET_A}
 N 160 -480 180 -480 {
-lab=NET_C}
+lab=NET_D}
 N 480 -480 530 -480 {
-lab=NET_C}
+lab=#net1}
 N 180 -580 180 -480 {
-lab=NET_C}
+lab=NET_D}
 N 480 -580 480 -480 {
-lab=NET_C}
+lab=#net1}
 N 180 -580 300 -580 {
-lab=NET_C}
+lab=NET_D}
 N 360 -580 480 -580 {
-lab=NET_C}
+lab=#net1}
 N 380 -480 480 -480 {
-lab=NET_C}
+lab=#net1}
 N 180 -480 300 -480 {
-lab=NET_C}
+lab=NET_D}
 N 380 -290 480 -290 {
-lab=NET_B}
+lab=NET_A}
 N 180 -290 300 -290 {
 lab=NET_A}
 N 610 -480 660 -480 {
-lab=#net1}
+lab=NET_E}
 N 660 -460 660 -400 {
-lab=#net1}
+lab=NET_E}
 N 660 -400 750 -400 {
-lab=#net1}
+lab=NET_E}
 N 660 -360 750 -360 {
 lab=NET_B}
 N 660 -360 660 -290 {
@@ -91,21 +91,21 @@ lab=NET_B}
 N 980 -380 1020 -380 {
 lab=NET_E}
 N 660 -460 760 -460 {
-lab=#net1}
+lab=NET_E}
 N 820 -460 980 -460 {
 lab=NET_E}
 N 980 -460 980 -380 {
 lab=NET_E}
 N 660 -480 660 -460 {
-lab=#net1}
+lab=NET_E}
 N 120 -420 160 -420 {
-lab=NET_C}
+lab=NET_D}
 N 160 -480 160 -420 {
-lab=NET_C}
+lab=NET_D}
 N 1560 -590 1680 -590 {
-lab=#net2}
+lab=NET_B}
 N 120 -480 160 -480 {
-lab=NET_C}
+lab=NET_D}
 N 1760 -590 1820 -590 {
 lab=NET_F}
 N 1210 -590 1480 -590 {
@@ -124,13 +124,13 @@ author="tcleval([
   return \{Stefan Schippers\}
 ])"
 }
-C {short.sym} 330 -390 0 0 {name=x2
+C {short.sym} 330 -390 1 0 {name=x2
 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
 }
 C {lab_pin.sym} 660 -290 0 1 {name=p5 sig_type=std_logic lab=NET_B}
 C {lab_show.sym} 480 -390 0 1 {name=l2 }
 C {lab_pin.sym} 60 -480 0 0 {name=p1 sig_type=std_logic lab=NET_C}
-C {short.sym} 330 -580 0 0 {name=x5
+C {short.sym} 330 -580 1 0 {name=x5
 spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
 }
 C {lab_show.sym} 480 -580 0 1 {name=l3 }
@@ -150,7 +150,7 @@ ROUT=1000}
 C {and_ngspice.sym} 790 -380 0 0 {name=x4 ROUT=1000 
 spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{false\}\} else \{return \{true\}\}])"
 }
-C {short.sym} 790 -460 0 0 {name=x1
+C {short.sym} 790 -460 1 0 {name=x1
 spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{true\}\} else \{return \{false\}\}])"
 }
 C {lab_show.sym} 1020 -380 0 1 {name=l4 }