diff --git a/src/save.c b/src/save.c
index b549c589..4445f20a 100644
--- a/src/save.c
+++ b/src/save.c
@@ -1038,6 +1038,18 @@ int raw_read(const char *f, Raw **rawptr, const char *type, int no_warning, doub
       dbg(0, "Raw file data read: %s\n", f);
       dbg(0, "points=%d, vars=%d, datasets=%d sim_type=%s\n", 
              raw->allpoints, raw->nvars, raw->datasets, raw->sim_type ? raw->sim_type : "<NULL>");
+
+      if(xctx->graph_flags & 4) { /* if cursor2 is enabled in first graph setup schematic annotation */
+        if(xctx->rects[GRIDLAYER] > 0)  {
+          xRect *r;
+          r = &xctx->rect[GRIDLAYER][0];
+          if(r->flags & 1) {
+            setup_graph_data(0, 0, &xctx->graph_struct);
+            backannotate_at_cursor_b_pos(r, &xctx->graph_struct);
+          }
+        }
+      }
+
     } else {
       /* free_rawfile(rawptr, 0, 0); */ /* do not free: already done in read_dataset()->extra_rawfile() */
       if(!no_warning) {
diff --git a/xschem_library/devices/ind.sym b/xschem_library/devices/ind.sym
index b645c028..913da636 100644
--- a/xschem_library/devices/ind.sym
+++ b/xschem_library/devices/ind.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.5 file_version=1.2
+v {xschem version=3.4.6 file_version=1.2
 *
 * This file is part of XSCHEM,
 * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -47,7 +47,7 @@ T {@#0:pinnumber} -10 -27.5 0 1 0.2 0.2 {layer=13}
 T {@#1:pinnumber} -10 17.5 0 1 0.2 0.2 {layer=13}
 T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance}
 T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance}
-T {@name} 15 -18.75 0 0 0.2 0.2 {}
-T {@value} 15 -3.75 0 0 0.2 0.2 {}
-T {m=@m} 15 11.25 0 0 0.2 0.2 {}
 T {@spice_get_current} -12.5 5 0 1 0.2 0.2 {layer=17}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -6.25 0 0 0.2 0.2 {}
+T {m=@m} 15 6.25 0 0 0.2 0.2 {}