From 17b09bc2030638a05b3c2a680cb024ace260345a Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Sun, 19 Jan 2025 13:00:43 +0100 Subject: [PATCH] add pin net_name attributes to some devices/ symbols --- xschem_library/devices/bus_tap.sym | 4 ++-- xschem_library/devices/connect.sym | 7 +++++-- xschem_library/devices/delay.sym | 7 +++++-- xschem_library/devices/diode.sym | 6 +++--- xschem_library/devices/flash_cell.sym | 8 ++++++-- xschem_library/devices/ic.sym | 3 ++- xschem_library/devices/nmos-sub.sym | 10 +++++++--- xschem_library/devices/nmos.sym | 5 ++++- xschem_library/devices/pmos-sub.sym | 10 +++++++--- xschem_library/devices/pmos.sym | 5 ++++- xschem_library/devices/pmoshv4.sym | 9 +++++++-- xschem_library/devices/pmosnat.sym | 8 ++++++-- xschem_library/devices/stop.sym | 1 + 13 files changed, 59 insertions(+), 24 deletions(-) diff --git a/xschem_library/devices/bus_tap.sym b/xschem_library/devices/bus_tap.sym index fc64553a..f62d9282 100644 --- a/xschem_library/devices/bus_tap.sym +++ b/xschem_library/devices/bus_tap.sym @@ -33,5 +33,5 @@ L 1 0 0 10 -10 {} B 5 9.375 -10.625 10.625 -9.375 {name=tap dir=inout} B 5 -0.625 -0.625 0.625 0.625 {name=bus dir=inout} T {@lab} 12.5 -12.5 3 0 0.27 0.27 {} -T {@#0:net_name} 41.25 -12.5 3 0 0.15 0.15 {layer=15 hide=instance} -T {@#0:spice_get_voltage} 31.25 -12.5 3 0 0.15 0.15 {layer=15 } +T {@#0:net_name} 31.25 -12.5 3 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:spice_get_voltage} 41.25 -12.5 3 0 0.15 0.15 {layer=15 } diff --git a/xschem_library/devices/connect.sym b/xschem_library/devices/connect.sym index 773613c9..78c76ac3 100644 --- a/xschem_library/devices/connect.sym +++ b/xschem_library/devices/connect.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=resistor +G {} +K {type=resistor format="@name @pinlist 0.01 m=@m" template="name=R1 m=1"} V {} @@ -43,3 +44,5 @@ L 4 -5 15 5 5 {} L 4 0 15 5 10 {} B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=out propag=1} B 5 -2.5 27.5 2.5 32.5 {name=m dir=in propag=0} +T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/delay.sym b/xschem_library/devices/delay.sym index 32e314ae..ba906ba4 100644 --- a/xschem_library/devices/delay.sym +++ b/xschem_library/devices/delay.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=delay_eldo +G {} +K {type=delay_eldo format="del@name @pinlist @del" template="name=d1 del=2e-9"} V {} @@ -35,3 +36,5 @@ B 5 -42.5 -2.5 -37.5 2.5 {name=inp dir=in} B 5 37.5 -2.5 42.5 2.5 {name=outp dir=out} T {del=@del} -27.5 -3.75 0 0 0.15 0.15 {} T {@name} -25 -22.5 0 0 0.2 0.2 {} +T {@#0:net_name} -40 -5 3 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} 30 -5 3 0 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/diode.sym b/xschem_library/devices/diode.sym index a6ffe7f7..eabffcb5 100644 --- a/xschem_library/devices/diode.sym +++ b/xschem_library/devices/diode.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -45,6 +45,6 @@ T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13} T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13} T {@name} 15 -18.75 0 0 0.2 0.2 {} T {@model} 15 -6.25 0 0 0.2 0.2 {} -T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15 hide=instance} -T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:net_name} 5 -28.75 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} 5 20 0 0 0.15 0.15 {layer=15 hide=instance} T {@spice_get_current} -12.5 -2.5 0 1 0.2 0.2 {layer=17} diff --git a/xschem_library/devices/flash_cell.sym b/xschem_library/devices/flash_cell.sym index fd89bc41..c8185e49 100644 --- a/xschem_library/devices/flash_cell.sym +++ b/xschem_library/devices/flash_cell.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -42,5 +42,9 @@ B 5 -2.5 -32.5 2.5 -27.5 {name=D dir=inout} B 5 -42.5 -2.5 -37.5 2.5 {name=G dir=in} B 5 -2.5 27.5 2.5 32.5 {name=S dir=inout} B 5 -2.5 -2.5 2.5 2.5 {name=B dir=in} -T {DVT=@dvt} -11 4 0 0 0.2 0.2 {} +T {DVT=@dvt} -11 9 0 0 0.2 0.2 {} T {@name} -10 -12 0 0 0.2 0.2 {} +T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#2:net_name} 5 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -45 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} +T {@#3:net_name} 5 0.625 0 0 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/ic.sym b/xschem_library/devices/ic.sym index 590b2d59..1a93e6c0 100644 --- a/xschem_library/devices/ic.sym +++ b/xschem_library/devices/ic.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.6RC file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -30,3 +30,4 @@ E {} L 4 -20 -20 0 0 {} B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in} T {IC=@value} -20 -20 2 0 0.3 0.3 {layer=4} +T {@#0:net_name} -15 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/nmos-sub.sym b/xschem_library/devices/nmos-sub.sym index d76f29da..129a8a42 100644 --- a/xschem_library/devices/nmos-sub.sym +++ b/xschem_library/devices/nmos-sub.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=nmos +G {} +K {type=nmos format="@name @pinlist @substrate @model w=@w l=@l m=@m" template="name=M1 model=nmos substrate=VSS w=5u l=0.18u m=1"} V {} @@ -43,4 +44,7 @@ B 5 17.5 27.5 22.5 32.5 {name=s dir=inout} T {@w\\/@l\\/@m} 7.5 -17.5 0 0 0.2 0.2 {} T {@name} 7.5 6.25 0 0 0.2 0.2 {} T {D} 25 -27.5 0 0 0.15 0.15 {} -T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=4} +T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=1} +T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/nmos.sym b/xschem_library/devices/nmos.sym index ccfdf0ea..144a16b3 100644 --- a/xschem_library/devices/nmos.sym +++ b/xschem_library/devices/nmos.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -53,3 +53,6 @@ T {@#1:pinnumber} -8.75 6.25 0 1 0.2 0.2 {layer=13} T {@device} 21.25 -11.25 0 0 0.2 0.2 {} T {@name} 21.25 3.75 0 0 0.2 0.2 {} T {D} 10 -17.5 0 0 0.2 0.2 {} +T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/pmos-sub.sym b/xschem_library/devices/pmos-sub.sym index cf14e591..516dde29 100644 --- a/xschem_library/devices/pmos-sub.sym +++ b/xschem_library/devices/pmos-sub.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=pmos +G {} +K {type=pmos format="@name @pinlist @substrate @model w=@w l=@l m=@m" template="name=M1 model=pmos substrate=VCC w=5u l=0.18u m=1"} V {} @@ -49,4 +50,7 @@ B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout} T {@w\\/@l\\/@m} 7.5 -17.5 0 0 0.2 0.2 {} T {@name} 7.5 6.25 0 0 0.2 0.2 {999} T {D} 25 20 0 0 0.15 0.15 {} -T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=4} +T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=1} +T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/pmos.sym b/xschem_library/devices/pmos.sym index 8b5f9cb6..1294855c 100644 --- a/xschem_library/devices/pmos.sym +++ b/xschem_library/devices/pmos.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -56,3 +56,6 @@ T {D} 7.5 8.75 0 0 0.2 0.2 {} T {@#2:pinnumber} 25 -28.75 0 0 0.2 0.2 {layer=13} T {@#0:pinnumber} 25 18.75 0 0 0.2 0.2 {layer=13} T {@#1:pinnumber} -13.75 6.25 0 1 0.2 0.2 {layer=13} +T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/pmoshv4.sym b/xschem_library/devices/pmoshv4.sym index d9b6d75f..c9ee55d3 100644 --- a/xschem_library/devices/pmoshv4.sym +++ b/xschem_library/devices/pmoshv4.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=pmos +G {} +K {type=pmos format="@name @pinlist @model w=@w l=@l number=@m" template="name=X1 model=tepbsim3 m=1 w=5u l=0.7u"} V {} @@ -44,3 +45,7 @@ T {@w\\/@l\\/@m} 7.5 5 0 0 0.25 0.2 {} T {@name} 7.5 -17.5 0 0 0.2 0.2 {999} T {HV} -20 -20 0 0 0.2 0.2 {} T {D} 11.875 23.125 0 0 0.15 0.15 {} +T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} +T {@#3:net_name} 25 1.25 0 0 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/pmosnat.sym b/xschem_library/devices/pmosnat.sym index e1aff7d8..699aee7d 100644 --- a/xschem_library/devices/pmosnat.sym +++ b/xschem_library/devices/pmosnat.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=pmos +G {} +K {type=pmos format="@name @pinlist vdd @model number=@m w=@w l=@l" template="name=X1 model=npbsim3 m=1 w=5u l=2u"} V {} @@ -46,3 +47,6 @@ B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in} B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout} T {@w\\/@l\\/@m} 12.5 -17.5 0 0 0.25 0.2 {} T {@name} 12.5 5 0 0 0.2 0.2 {} +T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15 hide=instance} +T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15 hide=instance} diff --git a/xschem_library/devices/stop.sym b/xschem_library/devices/stop.sym index 24195862..cb3d6aff 100644 --- a/xschem_library/devices/stop.sym +++ b/xschem_library/devices/stop.sym @@ -20,3 +20,4 @@ T {STOP} -60 -35 0 0 0.2 0.2 {} T {@@node @nodecond} -57.5 -15 0 0 0.2 0.2 {} T {time @timecond} -47.5 5 0 0 0.2 0.2 {} T {@name} 60 -35 0 1 0.2 0.2 {} +T {@#0:net_name} -72.5 -5 3 0 0.15 0.15 {layer=15 hide=instance}