diff --git a/doc/xschem_man/developer_info.html b/doc/xschem_man/developer_info.html
index e0971c46..ab0611f7 100644
--- a/doc/xschem_man/developer_info.html
+++ b/doc/xschem_man/developer_info.html
@@ -643,8 +643,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
exit [closewindow]
Exit the program, ask for confirm if current file modified.
if 'closewindow' is given close the window, otherwise leave with a blank schematic
- if 'force' is given do not ask before closing modified schematic windows/tabs
when closing the last remaining window
+ if 'force' is given do not ask before closing modified schematic windows/tabs
This command returns the list of remaining open windows in addition to main window
expandlabel lab
Expand vectored labels/instance names:
@@ -661,6 +661,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
if x0, y0 not given use mouse coordinates
flip_in_place
Flip selection horizontally, each object around its center
+ floaters_from_selected_inst
+ flatten to current level selected instance texts
fullscreen
Toggle fullscreen modes: fullscreen with menu & status, fullscreen, normal
get var
@@ -1045,8 +1047,8 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
xschem raw_query datasets: get number of datasets (simulation runs)
xschem raw_query value node n: return n-th value of 'node' in raw file
xschem raw_query loaded: return hierarchy level
- xschem raw_query rawfile: return raw filename
where raw file was loaded or -1 if no raw loaded
+ xschem raw_query rawfile: return raw filename
xschem raw_query index node: get index of simulation variable 'node'.
Example: raw_query index v(led) --> 46
xschem raw_query values node [dset] : print all simulation
diff --git a/src/save.c b/src/save.c
index cc687244..3995544c 100644
--- a/src/save.c
+++ b/src/save.c
@@ -964,7 +964,6 @@ int update_op()
int res = 0, p = 0, i;
tcleval("array unset ngspice::ngspice_data");
if(xctx->raw && xctx->raw->values) {
- tclsetvar("rawfile_loaded", "1");
xctx->raw->annot_p = 0;
for(i = 0; i < xctx->raw->nvars; ++i) {
char s[100];
diff --git a/src/scheduler.c b/src/scheduler.c
index ce2e051e..4114fe59 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -272,7 +272,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
my_snprintf(f, S(f), "%s/%s.raw", tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0));
}
tclsetboolvar("live_cursor2_backannotate", 1);
- tclsetvar("rawfile_loaded", "0");
extra_rawfile(3, NULL, NULL);
free_rawfile(&xctx->raw, 1);
raw_read(f, &xctx->raw, "op");
@@ -3136,7 +3135,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
else if(!strcmp(argv[1], "raw_clear"))
{
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
- tclsetvar("rawfile_loaded", "0");
extra_rawfile(3, NULL, NULL);
free_rawfile(&xctx->raw, 1);
Tcl_ResetResult(interp);
@@ -3148,8 +3146,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
* xschem raw_query datasets: get number of datasets (simulation runs)
* xschem raw_query value node n: return n-th value of 'node' in raw file
* xschem raw_query loaded: return hierarchy level
- * xschem raw_query rawfile: return raw filename
* where raw file was loaded or -1 if no raw loaded
+ * xschem raw_query rawfile: return raw filename
* xschem raw_query index node: get index of simulation variable 'node'.
* Example: raw_query index v(led) --> 46
* xschem raw_query values node [dset] : print all simulation
@@ -3248,7 +3246,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
tcleval("array unset ngspice::ngspice_data");
extra_rawfile(3, NULL, NULL);
free_rawfile(&xctx->raw, 1);
- tclsetvar("rawfile_loaded", "0");
} else if(argc > 2) {
extra_rawfile(3, NULL, NULL);
free_rawfile(&xctx->raw, 0);
@@ -3258,10 +3255,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc > 3) res = raw_read(f, &xctx->raw, argv[3]);
else res = raw_read(f, &xctx->raw, NULL);
if(sch_waves_loaded() >= 0) {
- tclsetvar("rawfile_loaded", "1");
draw();
}
- else tclsetvar("rawfile_loaded", "0");
}
Tcl_SetResult(interp, my_itoa(res), TCL_VOLATILE);
}
@@ -3284,10 +3279,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc > 2) raw_read_from_attr(&xctx->raw, argv[2]);
else raw_read_from_attr(&xctx->raw, NULL);
if(sch_waves_loaded() >= 0) {
- tclsetvar("rawfile_loaded", "1");
draw();
}
- else tclsetvar("rawfile_loaded", "0");
}
Tcl_ResetResult(interp);
}
@@ -4595,7 +4588,6 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(sch_waves_loaded() >= 0) {
extra_rawfile(3, NULL, NULL);
free_rawfile(&xctx->raw, 1);
- tclsetvar("rawfile_loaded", "0");
} else if(argc > 2) {
my_snprintf(f, S(f),"regsub {^~/} {%s} {%s/}", argv[2], home_dir);
tcleval(f);
@@ -4604,10 +4596,8 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
free_rawfile(&xctx->raw, 0);
table_read(f);
if(sch_waves_loaded() >= 0) {
- tclsetvar("rawfile_loaded", "1");
draw();
}
- else tclsetvar("rawfile_loaded", "0");
}
Tcl_ResetResult(interp);
}
diff --git a/src/xschem.tcl b/src/xschem.tcl
index ff1935a2..e6eed4cf 100644
--- a/src/xschem.tcl
+++ b/src/xschem.tcl
@@ -6200,7 +6200,7 @@ set tctx::global_list {
lvs_netlist measure_text netlist_dir netlist_show netlist_type no_ask_save
no_change_attrs nolist_libs noprint_libs old_selected_tok only_probes path pathlist
persistent_command preserve_unchanged_attrs prev_symbol ps_colors ps_paper_size rainbow_colors
- rawfile_loaded rcode recentfile
+ rcode recentfile
retval retval_orig rotated_text search_case search_exact search_found search_schematic
search_select search_value selected_tok show_hidden_texts show_infowindow
show_infowindow_after_netlist show_pin_net_names
@@ -6491,6 +6491,26 @@ proc switch_undo {} {
}
}
+proc load_raw {} {
+ global netlist_dir
+
+ set types {
+ {{Raw Files} {.raw} }
+ {{All Files} * }
+ }
+
+
+ set filename $netlist_dir/[file tail [file rootname [xschem get schname]]].raw
+ if { [xschem raw_query loaded] != -1} { ;# unload existing raw file(s)
+ xschem raw_clear
+ }
+ set filename [tk_getOpenFile -title "Select file" -multiple 0 -initialdir $netlist_dir \
+ -initialfile [file tail $filename] -filetypes $types]
+ if {[file exists $filename]} {
+ xschem raw_read $filename
+ }
+}
+
proc build_widgets { {topwin {} } } {
global XSCHEM_SHAREDIR tabbed_interface simulate_bg OS
global colors recentfile color_ps transparent_svg menu_debug_var enable_stretch
@@ -7048,9 +7068,11 @@ tclcommand=\"xschem raw_read \$netlist_dir/[file tail [file rootname [xschem get
}
$topwin.menubar.simulation.menu.graph add command -label "Annotate Operating Point into schematic" \
-command {set show_hidden_texts 1; xschem annotate_op}
- $topwin.menubar.simulation.menu.graph add checkbutton -variable rawfile_loaded \
- -label {Load/Unload spice .raw file} -command {
- xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
+ $topwin.menubar.simulation.menu.graph add command -label {Load spice .raw file} -command {
+ load_raw
+ }
+ $topwin.menubar.simulation.menu.graph add command -label {Unload spice .raw file} -command {
+ xschem raw_clear
}
$topwin.menubar.simulation.menu.graph add checkbutton -label "Live annotate probes with 'b' cursor" \
-variable live_cursor2_backannotate
@@ -7625,8 +7647,6 @@ if {$OS == "Windows"} {
set filetmp [pwd]/.tmp2
}
-set rawfile_loaded 0
-
# flag bound to a checkbutton in symbol editprop form
# if set cell is copied when renaming it
set_ne copy_cell 0
diff --git a/xschem_library/examples/mos_power_ampli.sch b/xschem_library/examples/mos_power_ampli.sch
index 288189f4..a3a9c29b 100644
--- a/xschem_library/examples/mos_power_ampli.sch
+++ b/xschem_library/examples/mos_power_ampli.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -96,6 +96,12 @@ T {@symname} 1320 -1350 0 1 0.8 0.8 {}
T {( @#0:resolved_net )} 120 -635 0 1 0.2 0.2 {name=p0 layer=15}
T {( @#0:resolved_net )} 120 -585 0 1 0.2 0.2 {name=p1 layer=15}
T {( @#0:resolved_net )} 1360 -665 0 1 0.2 0.2 {name=p5 layer=15}
+T {@name} 805 -486.25 2 0 0.2 0.2 {
+name=R11}
+T {@value} 783.75 -545 2 1 0.2 0.2 {
+name=R11}
+T {m=@m} 805 -501.25 2 0 0.2 0.2 {
+name=R11}
N 180 -590 180 -550 {lab=E9}
N 260 -550 340 -550 {lab=E9}
N 340 -590 340 -550 {lab=E9}
@@ -262,7 +268,8 @@ rload out 0 4
*.probe dc v(plus,vdc)
"}
C {lab_wire.sym} 920 -850 0 0 {name=l1 lab=GA}
-C {res.sym} 800 -530 1 1 {name=R11 m=1 value=1300 net_name=true}
+C {res.sym} 800 -530 1 1 {name=R11 m=1 value=1300 net_name=true
+hide_texts=true}
C {pnp.sym} 540 -580 0 0 {name=Q8 model=q2n2907p area=1 net_name=true}
C {capa.sym} 1240 -1020 0 0 {name=C12 m=1 value="40u" net_name=true}
C {diode.sym} 920 -1240 0 0 {name=D0 model=d1n4148 area=1
diff --git a/xschem_library/examples/ne555.sym b/xschem_library/examples/ne555.sym
index a517f6fe..5bdc8b50 100644
--- a/xschem_library/examples/ne555.sym
+++ b/xschem_library/examples/ne555.sym
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -42,10 +42,6 @@ L 4 60 120 80 120 {}
L 4 60 40 80 40 {}
L 4 -80 -40 -60 -40 {}
L 4 -60 -130 -20 -130 {}
-L 4 -20 -130 -10 -120 {}
-L 4 -10 -120 0 -120 {}
-L 4 0 -120 10 -120 {}
-L 4 10 -120 20 -130 {}
L 4 20 -130 60 -130 {}
L 4 -30 -10 -20 10 {}
L 4 -30 -10 -10 -10 {}
@@ -146,6 +142,7 @@ B 5 77.5 117.5 82.5 122.5 {name=CTRL dir=in }
B 5 77.5 37.5 82.5 42.5 {name=THRES dir=in }
B 5 77.5 -42.5 82.5 -37.5 {name=DIS dir=out }
B 5 77.5 -122.5 82.5 -117.5 {name=VCC dir=in }
+A 4 0 -135.8333333333333 20.83333333333334 196.260204708312 147.4795905833761 {}
T {@symname} -27.5 -111 0 0 0.3 0.3 {}
T {@name} 25 -152 0 0 0.2 0.2 {}
T {OUT} -35 26 0 1 0.2 0.2 {}
diff --git a/xschem_library/examples/test_ne555.sch b/xschem_library/examples/test_ne555.sch
index e1755193..540211de 100644
--- a/xschem_library/examples/test_ne555.sch
+++ b/xschem_library/examples/test_ne555.sch
@@ -1,4 +1,4 @@
-v {xschem version=3.4.4 file_version=1.2
+v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@@ -38,8 +38,9 @@ divx=5
subdivx=1
node="out
trig
-ctrl"
-color="4 15 7"
+\\"2/3 Vcc; ctrl\\"
+\\"1/3 Vcc; x1.18\\""
+color="4 15 7 12"
dataset=-1
unitx=1
logx=0