From 00311e7ff185548a88e080baf398cc575404d58d Mon Sep 17 00:00:00 2001 From: Stefan Frederik Date: Tue, 27 Jul 2021 16:42:54 +0200 Subject: [PATCH] update license info --- LICENSE | 2 +- README | 4 ++++ src/actions.c | 4 ++-- src/break.awk | 2 +- src/callback.c | 2 +- src/check.c | 2 +- src/clip.c | 2 +- src/convert_to_verilog2001.awk | 2 +- src/draw.c | 2 +- src/editprop.c | 2 +- src/expandlabel.y | 2 +- src/findnet.c | 2 +- src/flatten.awk | 2 +- src/flatten_savenodes.awk | 2 +- src/font.c | 2 +- src/globals.c | 2 +- src/hash_iterator.c | 2 +- src/hilight.c | 2 +- src/hspice_backannotate.tcl | 2 +- src/icon.c | 2 +- src/in_memory_undo.c | 2 +- src/main.c | 2 +- src/make_sym.awk | 2 +- src/make_sym_lcc.awk | 2 +- src/move.c | 2 +- src/netlist.c | 2 +- src/ngspice_backannotate.tcl | 2 +- src/node_hash.c | 2 +- src/options.c | 2 +- src/parselabel.l | 2 +- src/paste.c | 2 +- src/psprint.c | 2 +- src/rawtovcd.c | 2 +- src/save.c | 2 +- src/scheduler.c | 2 +- src/select.c | 2 +- src/spice.awk | 2 +- src/spice_netlist.c | 2 +- src/store.c | 2 +- src/svgdraw.c | 2 +- src/symgen.awk | 2 +- src/tedax.awk | 2 +- src/tedax_netlist.c | 2 +- src/token.c | 2 +- src/utile/clock.awk | 22 ++++++++++++++++++++++ src/utile/expand_alias.awk | 21 +++++++++++++++++++++ src/utile/param.awk | 21 +++++++++++++++++++++ src/utile/preprocess.awk | 21 +++++++++++++++++++++ src/utile/stimuli.awk | 21 +++++++++++++++++++++ src/utile/utile.tcl | 24 ++++++++++++++++++++++++ src/verilog.awk | 2 +- src/verilog_netlist.c | 2 +- src/vhdl.awk | 2 +- src/vhdl_netlist.c | 2 +- src/xinit.c | 2 +- src/xschem.h | 2 +- src/xschem.tcl | 4 ++-- tests/create_save.tcl | 2 +- tests/netlisting.tcl | 2 +- tests/open_close.tcl | 2 +- tests/run_regression.tcl | 2 +- tests/test_utility.tcl | 2 +- 62 files changed, 191 insertions(+), 57 deletions(-) diff --git a/LICENSE b/LICENSE index 1eab9a57..0a59697e 100644 --- a/LICENSE +++ b/LICENSE @@ -1,7 +1,7 @@ # This is a source file distribution of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/README b/README index 3a6ae08a..8ccb7c22 100644 --- a/README +++ b/README @@ -17,6 +17,10 @@ BUILDING & INSTALLING Please read the instructions in file INSTALL. +LICENSING + +See file LICENSE and license header in each source file. + SUBDIRECTORIES doc: xschem homepage, reference manual and man pages diff --git a/src/actions.c b/src/actions.c index 50bf71dc..22f68180 100644 --- a/src/actions.c +++ b/src/actions.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,7 +52,7 @@ void set_modify(int mod) void print_version() { printf("XSCHEM V%s\n", XSCHEM_VERSION); - printf("Copyright 1998-2020 Stefan Schippers\n"); + printf("Copyright 1998-2021 Stefan Schippers\n"); printf("\n"); printf("This is free software; see the source for copying conditions. There is NO\n"); printf("warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n"); diff --git a/src/break.awk b/src/break.awk index 18fd146a..cd6aada7 100755 --- a/src/break.awk +++ b/src/break.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/callback.c b/src/callback.c index 2105cba6..98d82f28 100644 --- a/src/callback.c +++ b/src/callback.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/check.c b/src/check.c index 5bc0a55a..884b0730 100644 --- a/src/check.c +++ b/src/check.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/clip.c b/src/clip.c index 83e3fc37..5c545b4e 100644 --- a/src/clip.c +++ b/src/clip.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/convert_to_verilog2001.awk b/src/convert_to_verilog2001.awk index fb9eae1d..7a8967a2 100755 --- a/src/convert_to_verilog2001.awk +++ b/src/convert_to_verilog2001.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/draw.c b/src/draw.c index 6f5656c0..1ff66966 100644 --- a/src/draw.c +++ b/src/draw.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/editprop.c b/src/editprop.c index 9c940796..43d9a609 100644 --- a/src/editprop.c +++ b/src/editprop.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/expandlabel.y b/src/expandlabel.y index 10b06c26..b812910b 100644 --- a/src/expandlabel.y +++ b/src/expandlabel.y @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/findnet.c b/src/findnet.c index 780efb62..15af0419 100644 --- a/src/findnet.c +++ b/src/findnet.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/flatten.awk b/src/flatten.awk index abdc9fee..8ddb87fa 100755 --- a/src/flatten.awk +++ b/src/flatten.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/flatten_savenodes.awk b/src/flatten_savenodes.awk index 488a8f61..7824dfba 100755 --- a/src/flatten_savenodes.awk +++ b/src/flatten_savenodes.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/font.c b/src/font.c index 48ebeba0..851c67c6 100644 --- a/src/font.c +++ b/src/font.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/globals.c b/src/globals.c index 06b5d2a2..8f35ef31 100644 --- a/src/globals.c +++ b/src/globals.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/hash_iterator.c b/src/hash_iterator.c index 5272597b..85c05597 100644 --- a/src/hash_iterator.c +++ b/src/hash_iterator.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/hilight.c b/src/hilight.c index d11fbed4..d6be5fbc 100644 --- a/src/hilight.c +++ b/src/hilight.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/hspice_backannotate.tcl b/src/hspice_backannotate.tcl index dfc2cd58..fc5e5125 100644 --- a/src/hspice_backannotate.tcl +++ b/src/hspice_backannotate.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/icon.c b/src/icon.c index 33a1a8b5..6aab0516 100644 --- a/src/icon.c +++ b/src/icon.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/in_memory_undo.c b/src/in_memory_undo.c index 3bb2ed4a..9cf85cee 100644 --- a/src/in_memory_undo.c +++ b/src/in_memory_undo.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/main.c b/src/main.c index b16b3c7f..da644b9b 100644 --- a/src/main.c +++ b/src/main.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/make_sym.awk b/src/make_sym.awk index c23a4731..26017cf1 100755 --- a/src/make_sym.awk +++ b/src/make_sym.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/make_sym_lcc.awk b/src/make_sym_lcc.awk index 4072ebaa..e62a0c4c 100644 --- a/src/make_sym_lcc.awk +++ b/src/make_sym_lcc.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/move.c b/src/move.c index 4cacca82..f220e499 100644 --- a/src/move.c +++ b/src/move.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/netlist.c b/src/netlist.c index 39cbfebb..4932e989 100644 --- a/src/netlist.c +++ b/src/netlist.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/ngspice_backannotate.tcl b/src/ngspice_backannotate.tcl index ad3ea53e..7cf67bea 100644 --- a/src/ngspice_backannotate.tcl +++ b/src/ngspice_backannotate.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/node_hash.c b/src/node_hash.c index 5f1f9019..33ce4b2c 100644 --- a/src/node_hash.c +++ b/src/node_hash.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/options.c b/src/options.c index 74521281..f9281b9b 100644 --- a/src/options.c +++ b/src/options.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/parselabel.l b/src/parselabel.l index 7de9740c..87e18f3a 100644 --- a/src/parselabel.l +++ b/src/parselabel.l @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/paste.c b/src/paste.c index 5bdaa373..5dadee61 100644 --- a/src/paste.c +++ b/src/paste.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/psprint.c b/src/psprint.c index 20f5f484..24d54b36 100644 --- a/src/psprint.c +++ b/src/psprint.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/rawtovcd.c b/src/rawtovcd.c index f27888b1..8e3de1dc 100644 --- a/src/rawtovcd.c +++ b/src/rawtovcd.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/save.c b/src/save.c index 6e39c953..b56484c7 100644 --- a/src/save.c +++ b/src/save.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/scheduler.c b/src/scheduler.c index 2bc99fa7..d4e0ba02 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/select.c b/src/select.c index 5e80be1b..87a34eb7 100644 --- a/src/select.c +++ b/src/select.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/spice.awk b/src/spice.awk index 18e4a9f4..e877b88d 100755 --- a/src/spice.awk +++ b/src/spice.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/spice_netlist.c b/src/spice_netlist.c index 1d4a480d..95677837 100644 --- a/src/spice_netlist.c +++ b/src/spice_netlist.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/store.c b/src/store.c index d705e41e..f0417837 100644 --- a/src/store.c +++ b/src/store.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/svgdraw.c b/src/svgdraw.c index 00a093b0..1256fafd 100644 --- a/src/svgdraw.c +++ b/src/svgdraw.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/symgen.awk b/src/symgen.awk index e4277013..dd67ada4 100755 --- a/src/symgen.awk +++ b/src/symgen.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/tedax.awk b/src/tedax.awk index a857a2b8..1f55f824 100755 --- a/src/tedax.awk +++ b/src/tedax.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/tedax_netlist.c b/src/tedax_netlist.c index 6192ee3b..b8d1e7a3 100644 --- a/src/tedax_netlist.c +++ b/src/tedax_netlist.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/token.c b/src/token.c index 1674e5c8..e42d50fa 100644 --- a/src/token.c +++ b/src/token.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/utile/clock.awk b/src/utile/clock.awk index ede9f0cc..e4b92284 100755 --- a/src/utile/clock.awk +++ b/src/utile/clock.awk @@ -1,4 +1,26 @@ #!/usr/bin/awk -f +# File: clock.awk +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + # # plugin for clock expansion # diff --git a/src/utile/expand_alias.awk b/src/utile/expand_alias.awk index aa4bdb0b..07f1b65c 100755 --- a/src/utile/expand_alias.awk +++ b/src/utile/expand_alias.awk @@ -1,4 +1,25 @@ #!/usr/bin/awk -f +# File: expand_alias.awk +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + # expand alias calls # expand nested aliases too # Stefan Schippers, 04-08-1999 diff --git a/src/utile/param.awk b/src/utile/param.awk index 8a9cf80b..4b87e73f 100755 --- a/src/utile/param.awk +++ b/src/utile/param.awk @@ -1,4 +1,25 @@ #!/usr/bin/awk -f +# File: param.awk +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + # 20200212 added simple expression parsing # 20170830 diff --git a/src/utile/preprocess.awk b/src/utile/preprocess.awk index 9cd7f57e..67bc2f9d 100755 --- a/src/utile/preprocess.awk +++ b/src/utile/preprocess.awk @@ -1,4 +1,25 @@ #!/usr/bin/awk -f +# File: preprocess.awk +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + # diff --git a/src/utile/stimuli.awk b/src/utile/stimuli.awk index a60f7252..6db7af9f 100755 --- a/src/utile/stimuli.awk +++ b/src/utile/stimuli.awk @@ -1,4 +1,25 @@ #!/usr/bin/awk -f +# File: stimuli.awk +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + # convert from Lsim like stimuli file to spice PWL form: # Stefan Schippers, 02-08-1999 # 04-08-1999: -bus notation is now supported diff --git a/src/utile/utile.tcl b/src/utile/utile.tcl index 5165b5e9..945ebc1d 100755 --- a/src/utile/utile.tcl +++ b/src/utile/utile.tcl @@ -1,4 +1,28 @@ #!/bin/sh + +# File: utile.tcl +# +# This file is part of XSCHEM, +# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit +# simulation. +# Copyright (C) 1998-2020 Stefan Frederik Schippers +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + + # the next line restarts using wish \ exec wish "$0" "$@" diff --git a/src/verilog.awk b/src/verilog.awk index 4b704a50..2124a20c 100755 --- a/src/verilog.awk +++ b/src/verilog.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/verilog_netlist.c b/src/verilog_netlist.c index 4eac6c39..1f8e60db 100644 --- a/src/verilog_netlist.c +++ b/src/verilog_netlist.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/vhdl.awk b/src/vhdl.awk index d762388c..009aec27 100755 --- a/src/vhdl.awk +++ b/src/vhdl.awk @@ -5,7 +5,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/vhdl_netlist.c b/src/vhdl_netlist.c index 5514fad2..4fd4685b 100644 --- a/src/vhdl_netlist.c +++ b/src/vhdl_netlist.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/xinit.c b/src/xinit.c index 724b061a..e9dfb847 100644 --- a/src/xinit.c +++ b/src/xinit.c @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/xschem.h b/src/xschem.h index 06aac1a8..69c8787a 100644 --- a/src/xschem.h +++ b/src/xschem.h @@ -3,7 +3,7 @@ * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. - * Copyright (C) 1998-2020 Stefan Frederik Schippers + * Copyright (C) 1998-2021 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/xschem.tcl b/src/xschem.tcl index caff5265..8bd28c70 100644 --- a/src/xschem.tcl +++ b/src/xschem.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -2037,7 +2037,7 @@ proc about {} { button .about.link -text {http://repo.hu/projects/xschem} -font Underline-Font -fg blue -relief flat button .about.link2 -text {https://github.com/StefanSchippers/xschem} -font Underline-Font -fg blue -relief flat button .about.link3 -text {Online XSCHEM Manual} -font Underline-Font -fg blue -relief flat - label .about.copyright -text "\n Copyright 1998-2020 Stefan Schippers (stefan.schippers@gmail.com) \n + label .about.copyright -text "\n Copyright 1998-2021 Stefan Schippers (stefan.schippers@gmail.com) \n This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE\n" button .about.close -text Close -command {destroy .about} -font {Sans 18} diff --git a/tests/create_save.tcl b/tests/create_save.tcl index 2f5c8b54..160a6726 100644 --- a/tests/create_save.tcl +++ b/tests/create_save.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/tests/netlisting.tcl b/tests/netlisting.tcl index 7ab7c7df..8e83404e 100644 --- a/tests/netlisting.tcl +++ b/tests/netlisting.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/tests/open_close.tcl b/tests/open_close.tcl index 7858a55d..8dbcfdae 100644 --- a/tests/open_close.tcl +++ b/tests/open_close.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/tests/run_regression.tcl b/tests/run_regression.tcl index e44c45fd..866ba1f1 100644 --- a/tests/run_regression.tcl +++ b/tests/run_regression.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/tests/test_utility.tcl b/tests/test_utility.tcl index e7a96e7a..6696769f 100644 --- a/tests/test_utility.tcl +++ b/tests/test_utility.tcl @@ -4,7 +4,7 @@ # This file is part of XSCHEM, # a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit # simulation. -# Copyright (C) 1998-2020 Stefan Frederik Schippers +# Copyright (C) 1998-2021 Stefan Frederik Schippers # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by