xschem/xschem_library/devices/lab_wire.sym

v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=label
format="*.alias @lab"
template="name=p1 sig_type=std_logic lab=xxx"
net_name=true}
V {}
S {}
E {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
T {@lab} -2.5 -1.25 2 0 0.27 0.27 {}
T {@spice_get_voltage} 1.875 10.15625 0 0 0.2 0.2 {vcenter=true layer=15}
fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net 2023-05-27 11:20:49 +02:00			`v {xschem version=3.4.0 file_version=1.2`
add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model. 2022-09-19 11:22:04 +02:00			`}`
			`G {}`
			`K {type=label`
populating xschem git repo 2020-08-08 15:47:34 +02:00			`format="*.alias @lab"`
fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net 2023-05-27 11:20:49 +02:00			`template="name=p1 sig_type=std_logic lab=xxx"`
			`net_name=true}`
populating xschem git repo 2020-08-08 15:47:34 +02:00			`V {}`
			`S {}`
			`E {}`
			`B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}`
			`T {@lab} -2.5 -1.25 2 0 0.27 0.27 {}`
eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded) 2022-10-24 17:28:39 +02:00			`T {@spice_get_voltage} 1.875 10.15625 0 0 0.2 0.2 {vcenter=true layer=15}`