19 lines
521 B
Plaintext
19 lines
521 B
Plaintext
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v {xschem version=2.9.5_RC5 file_version=1.1}
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G {
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Y <= not A after delay ;}
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V {assign #del Y=~A;}
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S {}
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E {}
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C {opin.sym} 550 -260 0 0 {name=p1 lab=Y verilog_type=wire}
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C {ipin.sym} 270 -260 0 0 {name=p2 lab=A}
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C {use.sym} 350 -560 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- use ieee.std_logic_arith.all;
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-- use ieee.std_logic_unsigned.all;
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-- library SYNOPSYS;
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-- use SYNOPSYS.ATTRIBUTES.ALL;
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}
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C {title.sym} 160 -30 0 0 {name=l2}
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