2020-08-08 15:47:34 +02:00
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<!DOCTYPE html>
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<html>
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<head>
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<title>COMPONENT INSTANTIATION</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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<a href="xschem_properties.html" class="prev">PREV</a>
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<a href="xschem_man.html" class="home">UP</a>
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<a href="symbol_property_syntax.html" class="next">NEXT</a>
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<!-- slide title -->
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<h1>COMPONENT INSTANTIATION</h1><br>
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<p>
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In the <a href="run_xschem.html">RUN XSCHEM</a> slide some instructions were provided as examples to
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place a component in the schematic. Now we will cover the topic in more detail with emphasis on
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component properties. Start by opening a test schematic window (you may delete any existing
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stuff in it if any).
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</p>
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<img src="load_schematic.png">
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<p>
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Now start by inserting a component, consider for example <kbd>devices/nmos4.sym</kbd>; press the
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<kbd>Insert</kbd> key, navigate to the <kbd>devices</kbd> design library and open the <kbd>nmos4.sym</kbd>
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symbol.
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</p>
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<img src="nmos4_symbol.png">
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<p>
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Now draw some wires on each pin of the nmos; place the mouse pointer on the component pins and
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use the <kbd>'w'</kbd> bindkey.
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</p>
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<img src="nmos4_wires.png">
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<p>
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we need now to put labels on wire ends: use the <kbd>Insert</kbd> key and locate the
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<kbd>devices/lab_pin.sym</kbd> symbol. After the <kbd>lab_pin</kbd> symbol is placed you can move it
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by selecting it with the mouse and pressing the <kbd>'m'</kbd> bindkey. You can also flip
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( <kbd>'F'</kbd>) and rotate while moving (<kbd>'R'</kbd>) to adjust the orientation. After
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placing the first one you may copy the others from it (<kbd>'c'</kbd> bindkey). The end result
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should look like this:
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</p>
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<img src="nmos4_labels.png">
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<p>
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This is what an electrical circuit is all about: a network of wires and components. In this
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schematic we have 5 components (4 labels and one mos) and 4 nets. It is not mandatory to put a
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wire segment between component pins; we could equally well do this:
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</p>
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<img src="nmos4_labels2.png">
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<p>
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This circuit is absolutely equivalent to the previous one: it will produce the same
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device connectivity netlist.<br>
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Now we need to set appropriate labels on the NMOS terminals. This is -again- accomplished with
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component properties. Select the wire label on the nmos source pin and press the <kbd>'q'</kbd>
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bindkey:
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</p>
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<img src="nmos4_editprop.png">
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<p>
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Now, replace the 'xxx' default string in the dialog with a different name (example: SOURCE)
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After clicking <kbd>OK</kbd> the source terminal will have the right label.
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</p>
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<img src="nmos4_editprop2.png">
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<p>
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repeat the process for the remaining GATE, DRAIN, BODY terminals;
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</p>
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<img src="nmos4_editprop3.png">
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<p>
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The following picture shows the <kbd>lab_pin</kbd> component with its properties and
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the corresponding symbol definition with its global properties (remember global properties in
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the <a href="xschem_properties.html">xschem_properties</a> slide)
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</p>
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<img src="properties.png" style="height:70%;">
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<p>
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when building the netlist XSCHEM will look for wires that touch the red square of the lab_pin
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component and name that wires with the component 'lab' property.
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for example the SPICE netlist of the circuit will be:
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<pre class="code">m1 DRAIN GATE SOURCE BODY nmos w=5u l=0.18u m=1</pre>
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</p>
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<p>
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We need now to edit the nmos properties. Select it and press the <kbd>'q'</kbd> bindkey
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</p>
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<img src="nmos_properties.png">
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<p>
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from the edit properties dialog you see there are 5 attributes with values defined:
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</p>
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<ul>
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<li> The component name <kbd>name=m1</kbd>.</li>
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<li> The spice model to be used in simulation <kbd>model=nmos</kbd>.</li>
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<li> The transistor width <kbd>w=5u</kbd>.</li>
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<li> The transistor channel length <kbd>l=0.18u</kbd>.</li>
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<li> The number of parallel transistors (multiplicity) <kbd>m=1</kbd>.</li>
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</ul>
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<p>
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We have never defined a value for these properties. These are the default values defined in the
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<kbd>template</kbd> attribute in the global <kbd>nmos4.sym</kbd> property string.
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</p>
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<img src="nmos_properties2.png">
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<p>
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We may want to change the dimensions of the transistor; simply change the <kbd>w</kbd> and
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<kbd>l</kbd> attribute values.<br>
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Also the component name may be changed as long as it is unique in the current schematic window.
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All simulators require that components are unique, it is not permitted to have 2 components
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with identical name, so XSCHEM enforces this.
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</p>
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<img src="nmos_properties3.png">
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<p>
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If a name is set that matches an existing component
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xschem will rename it keeping the first letter (<kbd>m</kbd> in this example) and appending a number
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(so you might end up in something like <kbd>m23</kbd> if there are many devices).
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</p>
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<p class="important">
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the <kbd>name</kbd> attribute is unique in the schematic window, and must be placed first in the
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property string. The name is also used by xschem to efficiently index it in the internal
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hash tables.
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</p><br>
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<h3>SPECIAL COMPONENTS</h3>
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<p>General purpose</p>
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<ul>
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<li><kbd>devices/ipin.sym</kbd></li>
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<li><kbd>devices/opin.sym</kbd></li>
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<li><kbd>devices/iopin.sym</kbd></li>
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<p>
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These components are used to name a net or a pin of another component. They do not have any other function
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other than giving an explicit name to a net.
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</p>
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<img src="special1.png">
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<li><kbd>devices/lab_pin.sym</kbd></li>
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<li><kbd>devices/lab_wire.sym</kbd></li>
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<li><kbd>devices/launcher.sym</kbd></li>
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<li><kbd>devices/architecture.sym</kbd><p> This prints global attributes of the schematic. Attributes of this
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symbol should not be set. It is a readonly symbol printing top-level schematic properties.</p></li>
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</ul>
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<p>Spice netlist special components</p>
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<ul>
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<li><kbd>devices/code.sym</kbd></li>
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<li><kbd>devices/code_shown.sym</kbd></li>
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<p> these symbols are used to place simulator commands or additional netlist lines as text into the schematic.</p>
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</ul>
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<p>Verilog netlist special components</p>
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<ul>
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<li><kbd>devices/verilog_timescale.sym</kbd></li>
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<li><kbd>devices/verilog_preprocessor.sym</kbd></li>
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</ul>
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<p>VHDL netlist special components</p>
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<ul>
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<li><kbd>devices/use.sym</kbd></li>
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<li><kbd>devices/package.sym</kbd></li>
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<li><kbd>devices/package_not_shown.sym</kbd></li>
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<li><kbd>devices/arch_declarations.sym</kbd></li>
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<li><kbd>devices/attributes.sym</kbd></li>
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<li><kbd>devices/port_attributes.sym</kbd></li>
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<li><kbd>devices/generic_pin.sym</kbd></li>
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2020-09-14 10:27:45 +02:00
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<li><kbd>devices/lab_generic.sym</kbd></li>
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2020-08-08 15:47:34 +02:00
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</ul><br>
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<!-- end of slide -->
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