v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=delay
verilog_ignore=true
vhdl_ignore=true
format="@name [ @@s ] [ @@d ] @adc_bridge_model"
template="name=A1 adc_bridge_model= adc_buff"
}
V {}
S {}
E {}
L 4 -30 0 30 0 {}
L 4 -10 -5 10 0 {}
L 4 -10 5 10 0 {}
B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propag=1}
B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propag=0}
T {@name} -25 -10 0 0 0.12 0.12 {}
T {@adc_bridge_model} 0 -10 0 0 0.12 0.12 {}
