v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {}
V {}
S {}
E {}
B 2 920 -580 1420 -190 {flags=graph 
y1 = -26
y2 = 12
divy = 7
subdivy=1
x1=0
x2=48
divx=8
  unitx=1


dataset=4


color=7
node=i(vload)}
B 2 920 -820 1420 -580 {flags=graph 
y1 = 0
y2 = 410
divy = 4
subdivy=1
x1=0
x2=48
divx=8
  unitx=1


dataset=4
color=4
node="\\"power; i(vload) v(plus) *\\""}
T {position the mouse close to one of the curves
and press 't' to display only that curve.
This allows you to annotate the active
waveform in the schematic.} 710 -150 0 0 0.3 0.3 {}
T {tcleval(SUN=[expr \{[xschem getprop rect 2 0 dataset] == -1 ? \{N/A\} : ([xschem getprop rect 2 0 dataset] + 1)*20\}]%)} 720 -540 0 0 0.4 0.4 {name=xxxx}
T {@name} 495 -766.25 2 1 0.2 0.2 {
name=Rs}
T {@value} 505 -726.25 2 0 0.2 0.2 {
name=Rs}
T {m=@m} 495 -781.25 2 1 0.2 0.2 {
name=Rs}
T {@spice_get_current} 416.25 -737.5 1 0 0.2 0.2 {layer=15
name=Rs}
T {SUNPOWER
MAXEON 3} -380 -510 0 0 0.4 0.4 {}
N 640 -560 640 -500 {
lab=minus}
N 640 -880 640 -860 {
lab=plus}
N 210 -750 210 -730 {
lab=A}
N 170 -750 210 -750 {
lab=A}
N 600 -690 600 -650 {
lab=0}
N 600 -750 600 -730 {
lab=B}
N 540 -750 540 -730 {
lab=B}
N 640 -680 640 -620 {
lab=im}
N 640 -800 640 -740 {
lab=ip}
N 110 -750 110 -730 {
lab=#net1}
N 110 -650 600 -650 {
lab=0}
N 80 -650 110 -650 {
lab=0}
N 110 -670 110 -650 {
lab=0}
N 210 -670 210 -650 {
lab=0}
N 340 -670 340 -650 {
lab=0}
N 540 -670 540 -650 {
lab=0}
N 340 -750 340 -730 {
lab=#net2}
N 340 -750 370 -750 {
lab=#net2}
N 210 -750 280 -750 {
lab=A}
N 430 -750 440 -750 {
lab=#net3}
N 530 -750 600 -750 {
lab=B}
N 500 -750 530 -750 {
lab=B}
C {code_shown.sym} 360 -420 0 0 {name=CONTROL_400w_voc_43
spice_ignore=false
only_toplevel=true
value=".param isc=11.5
.param n=60
.param area=0.01
.param rp=40
.param rs=0.002
.option savecurrents
vload plus minus 0
vsun fade 0 0
vref minus 0 0
.control
save all
dc vload 0 48 0.2 vsun 0.2 1.0 0.2
write pv_ngspice.raw 
quit
.endc
"}
C {iopin.sym} 640 -500 2 1 {name=p2 lab=minus}
C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers"}
C {ipin.sym} 100 -840 2 1 {name=p2 lab=fade}
C {ammeter.sym} 140 -750 3 0 {name=Vf}
C {iopin.sym} 640 -880 2 1 {name=p1 lab=plus}
C {launcher.sym} 1250 -160 0 0 {name=h3 
descr="Netlist, Simulate, Reload waves" 
tclcommand="
if \{![info exists sim]\} \{set_sim_defaults\}
set sim(spice,0,fg) 1
if \{[xschem raw_query loaded]\} \{ ;# Unload
  xschem raw_clear
\}
xschem netlist
xschem simulate
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
"
}
C {launcher.sym} 1250 -120 0 0 {name=h1 
descr="Load embedded waves" 
tclcommand="xschem raw_read_from_attr"
spice_data="
[encoded data, 117003 characters]
XBR9qQutwRQAAAAAAEhAAAAAAAAAAAAAAAAAAAAAABQAAAAAAEhAFAAAAAAASEAAAAAAAAAAAICJiQpUobDBgImJClShsMGAiYkKVKGwwQ=="}
C {launcher.sym} 1250 -70 0 0 {name=h2 
descr="Reload waves" 
tclcommand="
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
"
}
C {ammeter.sym} 640 -590 2 0 {name=Vm savecurrent=true}
C {ammeter.sym} 640 -830 2 0 {name=Vp savecurrent=true}
C {diode.sym} 210 -700 0 0 {name=D1 model=DPANEL area='area'

device_model=".model DPANEL D IS=1n N=1"}
C {res.sym} 340 -700 0 0 {name=Rp
value='rp'
footprint=1206
device=resistor
m=1}
C {res.sym} 470 -750 1 0 {name=Rs
value='rs'
footprint=1206
device=resistor
m=1
hide_texts=true}
C {lab_pin.sym} 80 -650 2 1 {name=l2 sig_type=std_logic lab=0}
C {cccs.sym} 540 -700 2 0 {name=F1 vnam=e1 value=1}
C {vcvs.sym} 640 -710 0 0 {name=E1 value="'n'"}
C {lab_wire.sym} 260 -750 0 0 {name=p3 sig_type=std_logic lab=A}
C {lab_wire.sym} 560 -750 0 0 {name=p4 sig_type=std_logic lab=B}
C {ammeter.sym} 130 -840 3 0 {name=Vf1}
C {lab_pin.sym} 160 -840 0 1 {name=p5 sig_type=std_logic lab=F}
C {bsource.sym} 110 -700 2 0 {name=B1 VAR=I FUNC="v(f) * isc"}
C {ammeter.sym} 310 -750 3 0 {name=Vr}
C {ammeter.sym} 400 -750 3 0 {name=Vm1 savecurrent=true}
C {code_shown.sym} 0 -410 0 0 {name=CONTROL_100w_voc_22
spice_ignore=true
only_toplevel=true
value=".param isc=6
.param n=36
.param area=1
.param rp=40
.param rs=0.002
.option savecurrents
vload plus minus 0
vsun fade 0 0
vref minus 0 0
.control
save all
dc vload 0 48 0.2 vsun 0.2 1.0 0.2
write pv_ngspice.raw 
quit
.endc
"}
C {lab_wire.sym} 640 -770 0 0 {name=p6 sig_type=std_logic lab=ip}
C {lab_wire.sym} 640 -640 0 0 {name=p7 sig_type=std_logic lab=im}
C {code_shown.sym} -410 -410 0 0 {name=CONTROL_395w_voc_75.4
spice_ignore=true
only_toplevel=true
value=".param isc=6.56
.param n=104
.param area=0.003
.param rp=3.5
.param rs=0.005
.option savecurrents
vload plus minus 0
vsun fade 0 0
vref minus 0 0
.control
save all
dc vload 0 80 0.2 vsun 0.2 1.0 0.2
write pv_ngspice.raw 
quit
.endc
"}
