v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=transmission_line
format="@name @pinlist z0=@z0 td=@td"
template="name=T1 z0=50 td=10n"}
V {}
S {}
E {}
L 4 -70 -15 70 -15 {}
L 4 -70 -5 70 -5 {}
L 4 -70 -5 -70 10 {}
L 4 -80 10 -70 10 {}
L 4 70 -5 70 10 {}
L 4 70 10 80 10 {}
L 4 -80 -10 80 -10 {}
B 5 -82.5 -12.5 -77.5 -7.5 {name=nap dir=in}
B 5 -82.5 7.5 -77.5 12.5 {name=nam dir=in}
B 5 77.5 -12.5 82.5 -7.5 {name=nbp dir=out}
B 5 77.5 7.5 82.5 12.5 {name=nbm dir=out}
T {z0=@z0 delay=@td} -60 -30 0 0 0.25 0.2 {}
T {@name} -40 -47.5 0 0 0.2 0.2 {}
