v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=none
template="name=S? device=none "
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}
T {gTAG-psu} 150 -100 0 1 0.333333 0.333333 { hcenter=true vcenter=true}
T {@name} 30 -190 2 1 0.333333 0.333333 {}

L 4 30 0 290 0 {}
L 4 290 -180 290 0 {}
L 4 30 -180 290 -180 {}
L 4 30 -180 30 0 {}







L 3 0 -60 30 -60 {}
B 5 -2.5 -62.5 2.5 -57.5 {name=jtag_power
pinnumber=1
pinseq=1
dir=inout
}
T {@#0:name} 40 -60 2 1 0.333333 0.333333 {}
L 3 290 -60 320 -60 {}
B 5 317.5 -62.5 322.5 -57.5 {pinnumber=2
pinseq=2
name=usb_power
dir=inout
}
T {@#1:name} 280 -60 2 0 0.333333 0.333333 {}
L 3 290 -20 320 -20 {}
B 5 317.5 -22.5 322.5 -17.5 {pinnumber=3
pinseq=3
name=pon_reset#
dir=inout
}
T {@#2:name} 280 -20 2 0 0.333333 0.333333 {}
