v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
K {type=symbol
template=""
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
format="@name @pinlist @value "

}
G {}
V {}
S {}
E {}


L 4 30 -50 50 -50 {}
L 4 50 -70 50 -30 {}
L 4 50 -55 70 -70 {}
L 4 50 -45 70 -30 {}

A 4 60 -50 30 0 360 {}


P 4 4 62 -32.5 70 -30 65 -37.5 62 -32.5 {fill=true}



L 3 70 -100 70 -70 {}
B 5 67.5 -102.5 72.5 -97.5 {pinnumber=1
pinseq=1
name=1
dir=inout
}
L 3 0 -50 30 -50 {}
B 5 -2.5 -52.5 2.5 -47.5 {pinnumber=2
pinseq=2
name=2
dir=inout
}
L 3 70 -30 70 0 {}
B 5 67.5 -2.5 72.5 2.5 {pinnumber=3
pinseq=3
name=3
dir=inout
}
