v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=launcher
format="** @descr : @url"
verilog_ignore=true
vhdl_ignore=true
spice_ignore=true
template="name=h1
descr=google 
url=www.google.com"}
V {}
S {}
E {}
P 4 9 -0 -0 -30 -12.5 -30 -5 -60 -5 -50 0 -60 5 -30 5 -30 12.5 -0 0 {fill=true}
T {@descr} 10 0 0 0 0.4 0.4 {vcenter=true}
