v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
function0="1 ~"
vhdl_stop=true
verilog_stop=true
format="@name @pinlist @VCCPIN @VSSPIN @symname wn=@wn lln=@lln wp=@wp lp=@lp m=@m"
template="name=x1 m=1 
+ wn=10u lln=1.2u wp=10u lp=1.2u 
+ VCCPIN=VCC VSSPIN=VSS"
extra="VCCPIN VSSPIN"
generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=string"
verilog_stop=true}
V {}
S {}
E {}
L 4 -40 0 -27.5 0 {}
L 4 -27.5 -20 -27.5 20 {}
L 4 -27.5 -20 16.25 0 {}
L 4 -27.5 20 16.25 0 {}
L 4 16.25 -2.5 16.25 2.5 {}
L 4 16.25 -2.5 18.75 -5 {}
L 4 18.75 -5 23.75 -5 {}
L 4 23.75 -5 26.25 -2.5 {}
L 4 26.25 -2.5 26.25 2.5 {}
L 4 23.75 5 26.25 2.5 {}
L 4 18.75 5 23.75 5 {}
L 4 16.25 2.5 18.75 5 {}
L 4 26.25 0 40 0 {}
B 5 37.5 -2.5 42.5 2.5 {name=y dir=out verilog_type=wire}
B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in goto=0}
T {n:@wn\\/@lln} -35 35 2 1 0.2 0.2 {}
T {p:@wp\\/@lp} -35 -22.5 2 1 0.2 0.2 {}
T {@name} -26.25 -5 0 0 0.2 0.2 {}
T {m=@m} -10 -37.5 2 1 0.25 0.2 {}
T {@symname} -6.25 10 0 0 0.2 0.2 {}
