v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 val=4.5 conduct=10.0"
generic_type="conduct=real val=real"}
V {}
S {}
E {}
L 4 -80 -10 70 -10 {}
L 4 -80 10 70 10 {}
L 4 -80 -10 -80 10 {}
L 4 70 -10 70 10 {}
L 4 70 0 90 0 {}
L 4 -100 0 -80 0 {}
B 5 87.5 -2.5 92.5 2.5 {name=USC sig_type=rreal verilog_type=wire dir=inout }
B 5 -102.5 -2.5 -97.5 2.5 {name=ING sig_type=std_logic verilog_type=wire dir=in }
T {@symname} -48.75 -9.25 0 0 0.3 0.3 {}
T {@name} 75 -22 0 0 0.2 0.2 {}
T {USC} 65 -4 0 1 0.2 0.2 {}
T {ING} -75 -4 0 0 0.2 0.2 {}
T {conduct=@conduct
val=@val} -65 -36 0 0 0.2 0.2 {}
