v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=inv
format="@name @pinlist @value m=@m"
verilog_format="not #(@risedel , @falldel ) @name ( @#1 , @#0 );"
tedax_format="footprint @name @footprint
device @name @symname"
template="name=U1
device=7414
footprint=SO14"
risedel=100
falldel=200
numslots=6 
power=VCC 
ground=GND"
extra="power ground"
extra_pinnumber="14 7"}
V {}
S {}
E {}
L 4 -40 0 -25 0 {}
L 4 -25 -20 -25 20 {}
L 4 -25 -20 15 0 {}
L 4 -25 20 15 0 {}
L 4 25 0 40 0 {}
L 4 -22.5 7.5 -12.5 7.5 {}
L 4 -12.5 7.5 -2.5 -2.5 {}
L 4 -7.5 -2.5 2.5 -2.5 {}
L 4 -17.5 7.5 -7.5 -2.5 {}
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in pinnumber=1:3:5:9:11:13}
B 5 37.5 -2.5 42.5 2.5 {name=Z dir=out verilog_type=wire pinnumber=2:4:6:8:10:12}
A 4 20 0 5 180 360 {}
T {@name} -10 -22.5 0 0 0.2 0.2 {}
T {@#0:pinnumber} -27.5 5 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} 27.5 5 0 0 0.2 0.2 {layer=13}
T {@device} -10 17.5 0 0 0.2 0.2 {}
