v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=probe
vhdl_ignore=true
spice_ignore=false
verilog_ignore=true
tedax_ignore=true
format=".save @attrs v( @@p )"
template="name=p1 attrs=\\"\\""}
V {}
S {}
E {}
L 15 3.75 -8.75 10 -16.25 {}
L 15 0 -0 3.75 -8.75 {}
L 15 10 -27.5 10 -13.75 {}
L 15 7.5 -16.25 28.75 -16.25 {}
L 15 12.5 -20 17.5 -20 {}
L 15 17.5 -23.75 17.5 -20 {}
L 15 17.5 -23.75 21.25 -23.75 {}
L 15 21.25 -23.75 21.25 -20 {}
L 15 21.25 -20 25 -20 {}
L 15 25 -23.75 25 -20 {}
L 15 25 -23.75 27.8125 -23.75 {}
B 5 -0.46875 -0.46875 0.46875 0.46875 {name=p dir=xxx}
