v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=parax_cap
format="@name @pinlist @gnd @value m=@m"
verilog_ignore=true
template="name=C1 gnd=0 value=4f m=1"}
V {}
S {}
E {}
L 4 0 -10 0 0 {}
L 4 -5 0 5 0 {}
L 4 -5 5 5 5 {}
L 4 0 5 0 12.5 {}
L 4 -2.5 12.5 2.5 12.5 {}
L 4 -2.5 12.5 0 15 {}
L 4 0 15 2.5 12.5 {}
B 5 -2.5 -12.5 2.5 -7.5 {name=p dir=in}
T {@value} 10 13.75 0 0 0.2 0.15 {}
T {@name} 10 3.75 0 0 0.2 0.15 {}
T {@gnd} -5 7.5 0 1 0.2 0.15 {}
T {m=@m} 10 -6.25 0 0 0.2 0.15 {}
T {@#0:net_name} 5 -22.5 0 0 0.15 0.15 {layer=15}
