v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -80 -40 -60 -40 {}
L 4 60 -40 80 -40 {}
L 4 -80 0 -60 0 {}
L 4 60 0 80 0 {}
L 4 60 40 80 40 {}
L 4 60 80 80 80 {}
L 4 -25 55 25 55 {}
L 4 -25 70 25 70 {}
L 4 -25 -25 25 -10 {}
L 4 -25 -10 25 -25 {}
B 5 -82.5 -42.5 -77.5 -37.5 {name=A dir=inout}
B 5 77.5 -42.5 82.5 -37.5 {name=B dir=inout }
B 5 -82.5 -2.5 -77.5 2.5 {name=B dir=inout}
B 5 77.5 -2.5 82.5 2.5 {name=A dir=inout }
B 5 77.5 37.5 82.5 42.5 {name=A dir=inout }
B 5 77.5 77.5 82.5 82.5 {name=B dir=inout }
P 4 5 -60 -60 -60 100 60 100 60 -60 -60 -60 {}
T {@symname} -0.5 -56 0 0 0.3 0.3 {hcenter=true}
T {@name} 0 83 0 1 0.2 0.2 {hcenter=true}
T {A} -55 -44 0 0 0.2 0.2 {}
T {B} 55 -44 0 1 0.2 0.2 {}
T {B} -55 -4 0 0 0.2 0.2 {}
T {A} 55 -4 0 1 0.2 0.2 {}
T {A} 55 36 0 1 0.2 0.2 {}
T {B} 55 76 0 1 0.2 0.2 {}
