39 lines
771 B
Systemverilog
39 lines
771 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef int T;
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module test;
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task t1;
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input [15:0] bad1;
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shortint bad1; // <--- Error (type doesn't match above)
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endtask
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task t2;
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input [31:0] bad2;
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T bad2; // <--- Error (type doesn't match above)
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endtask
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task t3;
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input [7:0] bad3;
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reg [3:0] bad3; // <--- Error (type doesn't match above)
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endtask
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task t4;
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input [7:0] bad4;
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reg bad4;
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reg bad4; // <--- Error (duplicate)
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endtask
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task t5;
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input [7:0] bad5;
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input [7:0] bad5; // <--- Error (duplicate)
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reg bad5;
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endtask
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endmodule
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