39 lines
892 B
Systemverilog
39 lines
892 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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// Checks that descendants pick up the proper library (IEEE 1800-2023 33.4.1.5)
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module sub;
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class C;
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static task info;
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$display("%s.C %%m=%m %%l=%l", `STRINGIFY(m));
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endtask
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endclass
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initial $display("%s %%m=%m %%l=%l", `STRINGIFY(m));
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initial C::info();
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endmodule
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`define DECL_MODULE(m) \
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module m; \
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sub sub(); \
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initial $display("%s %%m=%m %%l=%l", `STRINGIFY(m)); \
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endmodule
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`DECL_MODULE(m10)
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`DECL_MODULE(m20)
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`DECL_MODULE(m21)
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`DECL_MODULE(m22)
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`DECL_MODULE(m23)
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`DECL_MODULE(m24)
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`DECL_MODULE(m30)
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`DECL_MODULE(m31)
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`DECL_MODULE(m32)
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`DECL_MODULE(m40)
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`DECL_MODULE(m41)
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`DECL_MODULE(m42)
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`DECL_MODULE(m43)
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