77 lines
2.1 KiB
Systemverilog
77 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Tests: static/type-level get_coverage() with multiple instances,
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// progressive coverage queries via get_inst_coverage(), and dynamic
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// instance creation (including nested-scope instances).
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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// cg: three bins; used for multiple-instance and progressive-query tests
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covergroup cg;
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coverpoint data {bins low = {[0 : 1]}; bins mid = {[2 : 3]}; bins high = {[4 : 5]};}
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endgroup
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// cg2: two bins; used for dynamic (new) instance creation test
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covergroup cg2;
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coverpoint data {bins low = {[0 : 1]}; bins high = {[2 : 3]};}
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endgroup
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int data;
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initial begin
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// Declare all handles before any statements
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cg cg1, cg2_unused, cg3, cg_q;
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cg2 dyn_inst;
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// Multiple static instances: each samples a different bin
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cg1 = new;
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cg2_unused = new;
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cg3 = new;
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data = 0;
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cg1.sample(); // low
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data = 2;
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cg2_unused.sample(); // mid
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data = 4;
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cg3.sample(); // high
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// Progressive coverage query via get_inst_coverage()
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cg_q = new;
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data = 0;
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cg_q.sample();
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// 1/3 bins hit -> 33.3% (not an exact binary fraction; validate progression, not exact value)
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data = 2;
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cg_q.sample();
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// 2/3 bins hit -> 66.7%
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data = 4;
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cg_q.sample();
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`checkr(cg_q.get_inst_coverage(), 100.0); // 3/3 bins hit
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// Dynamic instance creation (from t_covergroup_dynamic)
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dyn_inst = new;
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data = 0;
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dyn_inst.sample(); // low
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data = 2;
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dyn_inst.sample(); // high
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begin
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cg2 dyn2;
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dyn2 = new;
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data = 0;
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dyn2.sample(); // low
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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