46 lines
1.6 KiB
Systemverilog
46 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
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// verilog_format: on
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module t;
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const static int a1;
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const static int a2 = 0;
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const automatic int b1;
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const automatic int b2 = 0;
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initial begin
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const static int c1;
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const static int c2 = 0;
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const automatic int d1;
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const automatic int d2 = 0;
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end
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function static void tb_func1();
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const static int e1;
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const static int e2 = 0;
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const automatic int f1;
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const automatic int f2 = 0;
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endfunction
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function automatic void tb_func2();
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const static int g1;
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const static int g2 = 0;
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const automatic int h1;
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const automatic int h2 = 0;
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endfunction
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endmodule
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