41 lines
970 B
Systemverilog
41 lines
970 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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for (int i = 0; i < 10; i++) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (i > 0 && result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class C;
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int que[$] = '{3, 4, 5};
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int arr[3] = '{5, 6, 7};
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rand int x, y;
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constraint distrib {
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x dist {que};
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y dist {arr};
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};
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endclass
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module t;
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initial begin
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C c = new;
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`check_rand(c, c.x, 3 <= c.x && c.x <= 5);
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`check_rand(c, c.y, 5 <= c.y && c.y <= 7);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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