[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:47: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:47: Verilog $stop
Aborting...